Search

Arvind Talukdar

Examiner (ID: 7677, Phone: (571)270-3177 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2189, 2132
Total Applications
676
Issued Applications
519
Pending Applications
63
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16408624 [patent_doc_number] => 10817176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Compute offload in block storage using virtual objects [patent_app_type] => utility [patent_app_number] => 16/011280 [patent_app_country] => US [patent_app_date] => 2018-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8353 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011280 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/011280
Compute offload in block storage using virtual objects Jun 17, 2018 Issued
Array ( [id] => 13511755 [patent_doc_number] => 20180307420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => SMART MEMORY BUFFERS [patent_app_type] => utility [patent_app_number] => 16/011187 [patent_app_country] => US [patent_app_date] => 2018-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/011187
Smart memory buffers Jun 17, 2018 Issued
Array ( [id] => 17636936 [patent_doc_number] => 11347660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Sub-realms [patent_app_type] => utility [patent_app_number] => 16/623528 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 35 [patent_no_of_words] => 36428 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16623528 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/623528
Sub-realms Jun 10, 2018 Issued
Array ( [id] => 18855648 [patent_doc_number] => 11853226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Address translation cache with use of page size information to select an invalidation lookup mode, or use of leaf-and-intermediate exclusive range-specifying invalidation request, or use of invalidation request specifying single address and page size information [patent_app_type] => utility [patent_app_number] => 16/624430 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10567 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16624430 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/624430
Address translation cache with use of page size information to select an invalidation lookup mode, or use of leaf-and-intermediate exclusive range-specifying invalidation request, or use of invalidation request specifying single address and page size information May 14, 2018 Issued
Array ( [id] => 13347049 [patent_doc_number] => 20180225064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => SYNCHRONIZING A CURSOR BASED ON CONSUMER AND PRODUCER THROUGHPUTS [patent_app_type] => utility [patent_app_number] => 15/945216 [patent_app_country] => US [patent_app_date] => 2018-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945216 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/945216
Synchronizing a cursor based on consumer and producer throughputs Apr 3, 2018 Issued
Array ( [id] => 14161847 [patent_doc_number] => 20190108026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => HANDLING EFFECTIVE ADDRESS SYNONYMS IN A LOAD-STORE UNIT THAT OPERATES WITHOUT ADDRESS TRANSLATION [patent_app_type] => utility [patent_app_number] => 15/825532 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825532 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825532
Handling effective address synonyms in a load-store unit that operates without address translation Nov 28, 2017 Issued
Array ( [id] => 14161845 [patent_doc_number] => 20190108025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => HANDLING EFFECTIVE ADDRESS SYNONYMS IN A LOAD-STORE UNIT THAT OPERATES WITHOUT ADDRESS TRANSLATION [patent_app_type] => utility [patent_app_number] => 15/825494 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825494 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825494
Handling effective address synonyms in a load-store unit that operates without address translation Nov 28, 2017 Issued
Array ( [id] => 14161849 [patent_doc_number] => 20190108027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => EFFECTIVE ADDRESS BASED LOAD STORE UNIT IN OUT OF ORDER PROCESSORS [patent_app_type] => utility [patent_app_number] => 15/825588 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825588 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825588
Effective address based load store unit in out of order processors Nov 28, 2017 Issued
Array ( [id] => 12611562 [patent_doc_number] => 20180095684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => REPLICATING TRACKS FROM A FIRST STORAGE SITE TO A SECOND AND THIRD STORAGE SITES [patent_app_type] => utility [patent_app_number] => 15/817087 [patent_app_country] => US [patent_app_date] => 2017-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15817087 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/817087
Replicating tracks from a first storage site to a second and third storage sites Nov 16, 2017 Issued
Array ( [id] => 13830577 [patent_doc_number] => 20190018773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => SELECTIVE DOWNSTREAM CACHE PROCESSING FOR DATA ACCESS [patent_app_type] => utility [patent_app_number] => 15/813751 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813751 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813751
Selective downstream cache processing for data access Nov 14, 2017 Issued
Array ( [id] => 14314425 [patent_doc_number] => 20190146916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => CONCURRENT MODIFICATION OF SHARED CACHE LINE BY MULTIPLE PROCESSORS [patent_app_type] => utility [patent_app_number] => 15/809049 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809049 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809049
Concurrent modification of shared cache line by multiple processors Nov 9, 2017 Issued
Array ( [id] => 13449157 [patent_doc_number] => 20180276121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => DISTRIBUTED GARBAGE COLLECTION FOR UNBALANCED WORKLOAD [patent_app_type] => utility [patent_app_number] => 15/808571 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808571 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808571
DISTRIBUTED GARBAGE COLLECTION FOR UNBALANCED WORKLOAD Nov 8, 2017 Abandoned
Array ( [id] => 12891439 [patent_doc_number] => 20180188988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => PARTIAL PAGE ACCESS IN A LOW POWER MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/808739 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808739 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808739
PARTIAL PAGE ACCESS IN A LOW POWER MEMORY SYSTEM Nov 8, 2017 Abandoned
Array ( [id] => 12221886 [patent_doc_number] => 20180060246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'LINEAR TO PHYSICAL ADDRESS TRANSLATION WITH SUPPORT FOR PAGE ATTRIBUTES' [patent_app_type] => utility [patent_app_number] => 15/803244 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4133 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803244 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/803244
Linear to physical address translation with support for page attributes Nov 2, 2017 Issued
Array ( [id] => 15702967 [patent_doc_number] => 10607670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Memory components and controllers that calibrate multiphase synchronous timing references [patent_app_type] => utility [patent_app_number] => 15/794177 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11433 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794177 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794177
Memory components and controllers that calibrate multiphase synchronous timing references Oct 25, 2017 Issued
Array ( [id] => 12207514 [patent_doc_number] => 20180052740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'OPTIMIZATION TO PERMIT BLOCK BASED INCREMENTAL BACKUP ACROSS SYSTEM REBOOT OR CRASH' [patent_app_type] => utility [patent_app_number] => 15/730089 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2415 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15730089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/730089
Optimization to permit block based incremental backup across system reboot or crash Oct 10, 2017 Issued
Array ( [id] => 13432709 [patent_doc_number] => 20180267897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/726489 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726489 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726489
MEMORY SYSTEM AND OPERATING METHOD THEREOF Oct 5, 2017 Abandoned
Array ( [id] => 12796774 [patent_doc_number] => 20180157427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/726460 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726460
Memory system and operating method thereof Oct 5, 2017 Issued
Array ( [id] => 15700829 [patent_doc_number] => 10606590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Effective address based load store unit in out of order processors [patent_app_type] => utility [patent_app_number] => 15/726522 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 16692 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726522 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726522
Effective address based load store unit in out of order processors Oct 5, 2017 Issued
Array ( [id] => 15700831 [patent_doc_number] => 10606591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Handling effective address synonyms in a load-store unit that operates without address translation [patent_app_type] => utility [patent_app_number] => 15/726596 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 16785 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726596 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726596
Handling effective address synonyms in a load-store unit that operates without address translation Oct 5, 2017 Issued
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