Search

Arvind Talukdar

Examiner (ID: 6525, Phone: (571)270-3177 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2189, 2182, 2132
Total Applications
659
Issued Applications
505
Pending Applications
75
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19347486 [patent_doc_number] => 20240256449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => TRACKING MEMORY MODIFICATIONS AT CACHE LINE GRANULARITY [patent_app_type] => utility [patent_app_number] => 18/629269 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629269 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629269
Tracking memory modifications at cache line granularity Apr 7, 2024 Issued
Array ( [id] => 20281920 [patent_doc_number] => 20250307162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Cache Data Distribution for a Stacked Die Configuration [patent_app_type] => utility [patent_app_number] => 18/621610 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621610 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621610
Cache Data Distribution for a Stacked Die Configuration Mar 28, 2024 Pending
Array ( [id] => 19917462 [patent_doc_number] => 12292831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Enhanced data reliability in multi-level memory cells [patent_app_type] => utility [patent_app_number] => 18/616993 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 16785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18616993 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/616993
Enhanced data reliability in multi-level memory cells Mar 25, 2024 Issued
Array ( [id] => 19963310 [patent_doc_number] => 12332811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-17 [patent_title] => Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access management [patent_app_type] => utility [patent_app_number] => 18/610087 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 25357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610087 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610087
Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access management Mar 18, 2024 Issued
Array ( [id] => 19235914 [patent_doc_number] => 20240193109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/444379 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8069 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444379
APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER Feb 15, 2024 Pending
Array ( [id] => 19834315 [patent_doc_number] => 20250086101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => STORAGE DEVICE PERFORMING ASYNCHRONOUS EVENT REPORTING, COMPUTER SYSTEM AND EVENT REPORTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/441072 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441072
STORAGE DEVICE PERFORMING ASYNCHRONOUS EVENT REPORTING, COMPUTER SYSTEM AND EVENT REPORTING METHOD THEREOF Feb 13, 2024 Pending
Array ( [id] => 19864719 [patent_doc_number] => 20250103505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => METHOD OF OPERATING MEMORY SYSTEM, CONTROLLER, MEMORY SYSTEM, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/442046 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442046 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/442046
METHOD OF OPERATING MEMORY SYSTEM, CONTROLLER, MEMORY SYSTEM, AND ELECTRONIC DEVICE Feb 13, 2024 Pending
Array ( [id] => 19772087 [patent_doc_number] => 20250053513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => OPPORTUNISTIC CLEANING OF COHERENCE DIRECTORIES TO REDUCE CACHE-COHERENCE OVERHEAD [patent_app_type] => utility [patent_app_number] => 18/432630 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432630 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432630
OPPORTUNISTIC CLEANING OF COHERENCE DIRECTORIES TO REDUCE CACHE-COHERENCE OVERHEAD Feb 4, 2024 Pending
Array ( [id] => 19383144 [patent_doc_number] => 20240273014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA [patent_app_type] => utility [patent_app_number] => 18/430381 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430381 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430381
APPARATUSES, SYSTEMS, AND METHODS FOR STORING MEMORY METADATA Jan 31, 2024 Pending
Array ( [id] => 20095141 [patent_doc_number] => 20250225077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => ADDRESS TRANSLATION STRUCTURE FOR ACCELERATORS [patent_app_type] => utility [patent_app_number] => 18/408307 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408307 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408307
ADDRESS TRANSLATION STRUCTURE FOR ACCELERATORS Jan 8, 2024 Pending
Array ( [id] => 19874561 [patent_doc_number] => 12267440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Data availability in a storage network in the event of memory device failure [patent_app_type] => utility [patent_app_number] => 18/403005 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 40 [patent_no_of_words] => 29649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403005 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/403005
Data availability in a storage network in the event of memory device failure Jan 2, 2024 Issued
Array ( [id] => 20415582 [patent_doc_number] => 12498867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Storage device that secures a block for a stream or namespace and system having the storage device [patent_app_type] => utility [patent_app_number] => 18/400866 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 75 [patent_figures_cnt] => 75 [patent_no_of_words] => 27661 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400866
Storage device that secures a block for a stream or namespace and system having the storage device Dec 28, 2023 Issued
Array ( [id] => 19321205 [patent_doc_number] => 20240242751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => Protocol For Refresh Between A Memory Controller And A Memory Device [patent_app_type] => utility [patent_app_number] => 18/399096 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399096
Protocol for refresh between a memory controller and a memory device Dec 27, 2023 Issued
Array ( [id] => 19764582 [patent_doc_number] => 12222872 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-02-11 [patent_title] => Method and apparatus for generating a histogram [patent_app_type] => utility [patent_app_number] => 18/394477 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394477 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/394477
Method and apparatus for generating a histogram Dec 21, 2023 Issued
Array ( [id] => 20070789 [patent_doc_number] => 20250209011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => INTRODUCTION OF POISON TABLE IN DYNAMIC RANDOM ACCESS MEMORY IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/395284 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18395284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/395284
Introduction of poison table in dynamic random access memory in a memory system Dec 21, 2023 Issued
Array ( [id] => 20257889 [patent_doc_number] => 12430239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Methods and apparatus for sparse tensor storage for neural network accelerators [patent_app_type] => utility [patent_app_number] => 18/539955 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 16568 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18539955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/539955
Methods and apparatus for sparse tensor storage for neural network accelerators Dec 13, 2023 Issued
Array ( [id] => 19872617 [patent_doc_number] => 12265477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Hybrid victim cache and write miss buffer with fence operation [patent_app_type] => utility [patent_app_number] => 18/535162 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 26321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/535162
Hybrid victim cache and write miss buffer with fence operation Dec 10, 2023 Issued
Array ( [id] => 19235895 [patent_doc_number] => 20240193090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => CACHE STRUCTURE FOR HIGH PERFORMANCE HARDWARE BASED PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/532373 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18532373 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/532373
CACHE STRUCTURE FOR HIGH PERFORMANCE HARDWARE BASED PROCESSOR Dec 6, 2023 Pending
Array ( [id] => 19220010 [patent_doc_number] => 20240184714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => CryptoMMU for Enabling Scalable and Secure Access Control of Third-Party Accelerators [patent_app_type] => utility [patent_app_number] => 18/529669 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529669 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529669
CryptoMMU for Enabling Scalable and Secure Access Control of Third-Party Accelerators Dec 4, 2023 Pending
Array ( [id] => 19220009 [patent_doc_number] => 20240184713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => METHOD AND APPARATUS FOR MANAGING VIRTUAL MEMORY IN HETEROGENEOUS SYSTEM, AND STORAGE MEDIUM STORING INSTRUCTIONS TO PERFORM METHOD FOR MANAGING VIRTUAL MEMORY [patent_app_type] => utility [patent_app_number] => 18/529534 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18529534 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/529534
METHOD AND APPARATUS FOR MANAGING VIRTUAL MEMORY IN HETEROGENEOUS SYSTEM, AND STORAGE MEDIUM STORING INSTRUCTIONS TO PERFORM METHOD FOR MANAGING VIRTUAL MEMORY Dec 4, 2023 Pending
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