Search

Arvind Talukdar

Examiner (ID: 7677, Phone: (571)270-3177 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2182, 2189, 2132
Total Applications
676
Issued Applications
519
Pending Applications
63
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18847081 [patent_doc_number] => 20230409485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => FLEXIBLE CACHE ALLOCATION TECHNOLOGY PRIORITY-BASED CACHE LINE EVICTION ALGORITHM [patent_app_type] => utility [patent_app_number] => 18/321603 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321603
Flexible cache allocation technology priority-based cache line eviction algorithm May 21, 2023 Issued
Array ( [id] => 19398435 [patent_doc_number] => 12072797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Memory system and non-transitory computer readable recording medium [patent_app_type] => utility [patent_app_number] => 18/197667 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10586 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18197667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/197667
Memory system and non-transitory computer readable recording medium May 14, 2023 Issued
Array ( [id] => 19545130 [patent_doc_number] => 20240362166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => METHODS AND APPARATUS FOR INFLIGHT DATA FORWARDING AND INVALIDATION OF PENDING WRITES IN STORE QUEUE [patent_app_type] => utility [patent_app_number] => 18/305437 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 95357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305437
Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue Apr 23, 2023 Issued
Array ( [id] => 20166732 [patent_doc_number] => 20250258779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => MAINTENANCE OPERATIONS ACROSS SUBDIVIDED MEMORY DOMAINS [patent_app_type] => utility [patent_app_number] => 18/859251 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18859251 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/859251
MAINTENANCE OPERATIONS ACROSS SUBDIVIDED MEMORY DOMAINS Apr 20, 2023 Pending
Array ( [id] => 19522655 [patent_doc_number] => 12124378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-22 [patent_title] => Method for efficient grouping of cache requests for datapath scheduling [patent_app_type] => utility [patent_app_number] => 18/137421 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 38810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137421 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/137421
Method for efficient grouping of cache requests for datapath scheduling Apr 19, 2023 Issued
Array ( [id] => 19581593 [patent_doc_number] => 12147711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Memory system and method for controlling nonvolatile memory with a host memory buffer [patent_app_type] => utility [patent_app_number] => 18/301522 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 16878 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18301522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/301522
Memory system and method for controlling nonvolatile memory with a host memory buffer Apr 16, 2023 Issued
Array ( [id] => 19442931 [patent_doc_number] => 12093195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Techniques for command bus training to a memory device [patent_app_type] => utility [patent_app_number] => 18/134920 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134920 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134920
Techniques for command bus training to a memory device Apr 13, 2023 Issued
Array ( [id] => 20070777 [patent_doc_number] => 20250208999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/849140 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18849140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/849140
SEMICONDUCTOR DEVICE Apr 5, 2023 Pending
Array ( [id] => 18539670 [patent_doc_number] => 20230244778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => PHYSICALLY-TAGGED DATA CACHE MEMORY THAT USES TRANSLATION CONTEXT TO REDUCE LIKELIHOOD THAT ENTRIES ALLOCATED DURING EXECUTION UNDER ONE TRANSLATION CONTEXT ARE ACCESSIBLE DURING EXECUTION UNDER ANOTHER TRANSLATION CONTEXT [patent_app_type] => utility [patent_app_number] => 18/130093 [patent_app_country] => US [patent_app_date] => 2023-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18130093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/130093
Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context Apr 2, 2023 Issued
Array ( [id] => 20790187 [patent_doc_number] => 12664102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Memory management [patent_app_type] => utility [patent_app_number] => 18/859246 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 24862 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18859246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/859246
Memory management Mar 16, 2023 Issued
Array ( [id] => 19451157 [patent_doc_number] => 20240311287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SYSTEMS, METHODS, AND APPARATUSES FOR AUTO-SCALING VOLATILE MEMORY ALLOCATION IN AN ELECTRONIC NETWORK [patent_app_type] => utility [patent_app_number] => 18/122342 [patent_app_country] => US [patent_app_date] => 2023-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18122342 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/122342
Systems, methods, and apparatuses for auto-scaling volatile memory allocation in an electronic network Mar 15, 2023 Issued
Array ( [id] => 19764886 [patent_doc_number] => 12223177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Memory system and control method [patent_app_type] => utility [patent_app_number] => 18/182546 [patent_app_country] => US [patent_app_date] => 2023-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 8358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 483 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/182546
Memory system and control method Mar 12, 2023 Issued
Array ( [id] => 19391506 [patent_doc_number] => 20240281376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => DECOMPRESSING NON-CONTIGUOUS BLOCKS OF DATA USING INSTRUCTION-BASED DIRECT-MEMORY ACCESS (DMA) [patent_app_type] => utility [patent_app_number] => 18/171994 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18171994 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/171994
DECOMPRESSING NON-CONTIGUOUS BLOCKS OF DATA USING INSTRUCTION-BASED DIRECT-MEMORY ACCESS (DMA) Feb 20, 2023 Abandoned
Array ( [id] => 19413325 [patent_doc_number] => 12079141 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Hardware offloading for an emulated IOMMU device [patent_app_type] => utility [patent_app_number] => 18/170093 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170093 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170093
Hardware offloading for an emulated IOMMU device Feb 15, 2023 Issued
Array ( [id] => 18409758 [patent_doc_number] => 20230171111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => Data Availability in Vast Network in Event of Memory Device Failure [patent_app_type] => utility [patent_app_number] => 18/104382 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104382
Data availability in vast network in event of memory device failure Jan 31, 2023 Issued
Array ( [id] => 19347172 [patent_doc_number] => 20240256135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => Storage Management System and Method [patent_app_type] => utility [patent_app_number] => 18/162190 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162190 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162190
System and method using IOPS to service priority queues in a distributed manner Jan 30, 2023 Issued
Array ( [id] => 18832465 [patent_doc_number] => 20230400992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => METHOD FOR OPERATING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/101232 [patent_app_country] => US [patent_app_date] => 2023-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18101232 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/101232
Method for operating memory device Jan 24, 2023 Issued
Array ( [id] => 18333676 [patent_doc_number] => 20230125624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => NON-VOLATILE DUAL INLINE MEMORY MODULE (NVDIMM) FOR SUPPORTING DRAM CACHE MODE AND OPERATION METHOD OF NVDIMM [patent_app_type] => utility [patent_app_number] => 18/146054 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146054 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146054
Non-volatile dual inline memory module (NVDIMM) for supporting DRAM cache mode and operation method of NVDIMM Dec 22, 2022 Issued
Array ( [id] => 19251135 [patent_doc_number] => 20240202125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => COHERENCY BYPASS TAGGING FOR READ-SHARED DATA [patent_app_type] => utility [patent_app_number] => 18/084054 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084054 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/084054
COHERENCY BYPASS TAGGING FOR READ-SHARED DATA Dec 18, 2022 Pending
Array ( [id] => 18967203 [patent_doc_number] => 11900981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Protocol for refresh between a memory controller and a memory device [patent_app_type] => utility [patent_app_number] => 18/078934 [patent_app_country] => US [patent_app_date] => 2022-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078934 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078934
Protocol for refresh between a memory controller and a memory device Dec 9, 2022 Issued
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