Arvind Talukdar

Array ( [id] => 18333676 [patent_doc_number] => 20230125624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => NON-VOLATILE DUAL INLINE MEMORY MODULE (NVDIMM) FOR SUPPORTING DRAM CACHE MODE AND OPERATION METHOD OF NVDIMM [patent_app_type] => utility [patent_app_number] => 18/146054 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19251135 [patent_doc_number] => 20240202125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => COHERENCY BYPASS TAGGING FOR READ-SHARED DATA [patent_app_type] => utility [patent_app_number] => 18/084054 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18084054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18967203 [patent_doc_number] => 11900981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Protocol for refresh between a memory controller and a memory device [patent_app_type] => utility [patent_app_number] => 18/078934 [patent_app_country] => US [patent_app_date] => 2022-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18255100 [patent_doc_number] => 20230082139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => STORAGE DEVICE THAT SECURES A BLOCK FOR A STREAM OR NAMESPACE AND SYSTEM HAVING THE STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/987449 [patent_app_country] => US [patent_app_date] => 2022-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17987449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19107304 [patent_doc_number] => 11960408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Semiconductor memory device including unit page buffer blocks having four page buffer pairs [patent_app_type] => utility [patent_app_number] => 18/053003 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 8709 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18053003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18925480 [patent_doc_number] => 20240028484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => AUTOMATIC DISCOVERY OF APPLICATION RESOURCES FOR APPLICATION BACKUP IN A CONTAINER ORCHESTRATION PLATFORM [patent_app_type] => utility [patent_app_number] => 17/976898 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976898 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19022020 [patent_doc_number] => 20240078191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => SYSTEM AND METHOD FOR SECURING INDIRECT MEMORY ACCESSES [patent_app_type] => utility [patent_app_number] => 18/049683 [patent_app_country] => US [patent_app_date] => 2022-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18049683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303515 [patent_doc_number] => 20240232095 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA [patent_app_type] => utility [patent_app_number] => 17/972493 [patent_app_country] => US [patent_app_date] => 2022-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17972493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303515 [patent_doc_number] => 20240232095 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => MEMORY DEVICE HAVING CACHE STORING CACHE DATA AND SCRUB DATA [patent_app_type] => utility [patent_app_number] => 17/972493 [patent_app_country] => US [patent_app_date] => 2022-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17972493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18184384 [patent_doc_number] => 20230045114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => BUFFER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/966322 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17966322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18393483 [patent_doc_number] => 20230161703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => COMPUTING SYSTEM WITH WRITE-BACK AND INVALIDATION IN A HIERARCHICAL CACHE STRUCTURE BASED ON AT LEAST ONE DESIGNATED KEY IDENTIFICATION CODE [patent_app_type] => utility [patent_app_number] => 18/046618 [patent_app_country] => US [patent_app_date] => 2022-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18148031 [patent_doc_number] => 20230021888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => TECHNOLOGIES FOR ADDRESS TRANSLATION CACHE RESERVATION IN OFFLOAD DEVICES [patent_app_type] => utility [patent_app_number] => 17/958333 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17318 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19144585 [patent_doc_number] => 20240143502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => APPARATUS AND METHOD FOR A ZERO LEVEL CACHE/MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/958338 [patent_app_country] => US [patent_app_date] => 2022-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 58932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19069596 [patent_doc_number] => 20240104022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => MULTI-LEVEL CACHE DATA TRACKING AND ISOLATION [patent_app_type] => utility [patent_app_number] => 17/954232 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19114952 [patent_doc_number] => 20240126702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => HARDWARE PROCESSOR CORE HAVING A MEMORY SLICED BY LINEAR ADDRESS [patent_app_type] => utility [patent_app_number] => 17/949803 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 52608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18257416 [patent_doc_number] => 20230084456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => STORAGE DEVICE, STORAGE SYSTEM, AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/939976 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18651439 [patent_doc_number] => 20230297275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => MEMORY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 17/939745 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18997692 [patent_doc_number] => 11914533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Systems and methods for data prefetching for low latency data read from a remote server [patent_app_type] => utility [patent_app_number] => 17/939944 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11407 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18997692 [patent_doc_number] => 11914533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Systems and methods for data prefetching for low latency data read from a remote server [patent_app_type] => utility [patent_app_number] => 17/939944 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11407 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18997692 [patent_doc_number] => 11914533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Systems and methods for data prefetching for low latency data read from a remote server [patent_app_type] => utility [patent_app_number] => 17/939944 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11407 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939944 [rel_patent_id] =>[rel_patent_doc_number] =>)