Search

Arvind Talukdar

Examiner (ID: 6525, Phone: (571)270-3177 , Office: P/2132 )

Most Active Art Unit
2132
Art Unit(s)
2189, 2182, 2132
Total Applications
659
Issued Applications
505
Pending Applications
75
Abandoned Applications
109

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18772679 [patent_doc_number] => 20230367505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => SSD DEVICE FEATURING IMPROVED DECODING [patent_app_type] => utility [patent_app_number] => 17/663281 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663281
SSD device featuring improved decoding May 12, 2022 Issued
Array ( [id] => 18772895 [patent_doc_number] => 20230367721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => ADDRESS SCRAMBLING BY LINEAR MAPS IN GALOIS FIELDS [patent_app_type] => utility [patent_app_number] => 17/663121 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17663121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/663121
Address scrambling by linear maps in Galois fields May 11, 2022 Issued
Array ( [id] => 17811831 [patent_doc_number] => 20220263666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => Storing Error-Encoded Data Slices in Vast Network Based on Storage Requirements and Parameters [patent_app_type] => utility [patent_app_number] => 17/738244 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738244
Storing error-encoded data slices in vast network based on storage requirements and parameters May 5, 2022 Issued
Array ( [id] => 19045201 [patent_doc_number] => 11934311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Hybrid allocation of data lines in a streaming cache memory [patent_app_type] => utility [patent_app_number] => 17/736557 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15160 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736557
Hybrid allocation of data lines in a streaming cache memory May 3, 2022 Issued
Array ( [id] => 17794289 [patent_doc_number] => 20220253381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => MEMORY SYSTEM AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 17/731089 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731089 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731089
Memory system and non-transitory computer readable recording medium Apr 26, 2022 Issued
Array ( [id] => 18638172 [patent_doc_number] => 11762774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Arithmetic processor and method for operating arithmetic processor [patent_app_type] => utility [patent_app_number] => 17/725589 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12641 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725589 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725589
Arithmetic processor and method for operating arithmetic processor Apr 20, 2022 Issued
Array ( [id] => 20242690 [patent_doc_number] => 12423008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Reading a master boot record for a namespace using a regular read operation [patent_app_type] => utility [patent_app_number] => 17/726436 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8707 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726436 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726436
Reading a master boot record for a namespace using a regular read operation Apr 20, 2022 Issued
Array ( [id] => 18454057 [patent_doc_number] => 20230195337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => DUAL-LEVEL REFRESH MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/713652 [patent_app_country] => US [patent_app_date] => 2022-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713652 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713652
Dual-level refresh management Apr 4, 2022 Issued
Array ( [id] => 18023193 [patent_doc_number] => 20220374692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => INTERLEAVING MEMORY REQUESTS TO ACCELERATE MEMORY ACCESSES [patent_app_type] => utility [patent_app_number] => 17/713122 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713122
Interleaving memory requests to accelerate memory accesses Apr 3, 2022 Issued
Array ( [id] => 18765642 [patent_doc_number] => 11816040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Device memory protection for supporting trust domains [patent_app_type] => utility [patent_app_number] => 17/712109 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8194 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712109 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712109
Device memory protection for supporting trust domains Apr 1, 2022 Issued
Array ( [id] => 19099587 [patent_doc_number] => 20240118815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => DATA STORAGE SYSTEM AND METHOD FOR CONTROLLING ACCESS TO DATA STORED IN A DATA STORAGE [patent_app_type] => utility [patent_app_number] => 18/263179 [patent_app_country] => US [patent_app_date] => 2022-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18263179 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/263179
DATA STORAGE SYSTEM AND METHOD FOR CONTROLLING ACCESS TO DATA STORED IN A DATA STORAGE Mar 29, 2022 Pending
Array ( [id] => 18677974 [patent_doc_number] => 20230315621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => DISAGGREGATED HYPERVISOR ON MULTIPLE DEVICES [patent_app_type] => utility [patent_app_number] => 17/707538 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/707538
Disaggregated hypervisor on multiple devices Mar 28, 2022 Issued
Array ( [id] => 18950757 [patent_doc_number] => 11894060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Dual performance trim for optimization of non-volatile memory performance, endurance, and reliability [patent_app_type] => utility [patent_app_number] => 17/704434 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 19185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704434
Dual performance trim for optimization of non-volatile memory performance, endurance, and reliability Mar 24, 2022 Issued
Array ( [id] => 18802937 [patent_doc_number] => 11836094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Cryptographic data objects page conversion [patent_app_type] => utility [patent_app_number] => 17/699593 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 12564 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699593
Cryptographic data objects page conversion Mar 20, 2022 Issued
Array ( [id] => 18651672 [patent_doc_number] => 20230297508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => APPARATUS AND METHOD FOR HARDWARE-ACCELERATED TEXTURE LOOKUP AND INTERPOLATION [patent_app_type] => utility [patent_app_number] => 17/699067 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699067
APPARATUS AND METHOD FOR HARDWARE-ACCELERATED TEXTURE LOOKUP AND INTERPOLATION Mar 17, 2022 Pending
Array ( [id] => 18239244 [patent_doc_number] => 20230071555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MEMORY SYSTEM FOR DATA ENCRYPTION [patent_app_type] => utility [patent_app_number] => 17/653567 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 518 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17653567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/653567
Memory system for data encryption Mar 3, 2022 Issued
Array ( [id] => 17674873 [patent_doc_number] => 20220188040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => ADJUSTING SCAN EVENT THRESHOLDS TO MITIGATE MEMORY ERRORS [patent_app_type] => utility [patent_app_number] => 17/685102 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685102
Adjusting scan event thresholds to mitigate memory errors Mar 1, 2022 Issued
Array ( [id] => 18225609 [patent_doc_number] => 20230064603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES [patent_app_type] => utility [patent_app_number] => 17/675785 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/675785
SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES Feb 17, 2022 Abandoned
Array ( [id] => 18687087 [patent_doc_number] => 11782824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Universal data path architecture for different data array [patent_app_type] => utility [patent_app_number] => 17/667384 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667384
Universal data path architecture for different data array Feb 7, 2022 Issued
Array ( [id] => 18330794 [patent_doc_number] => 11636036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Unified memory management for a multiple processor system [patent_app_type] => utility [patent_app_number] => 17/587102 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587102
Unified memory management for a multiple processor system Jan 27, 2022 Issued
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