Search

Arvind Talukdar

Examiner (ID: 17867)

Most Active Art Unit
2132
Art Unit(s)
2189, 2182, 2132
Total Applications
666
Issued Applications
515
Pending Applications
61
Abandoned Applications
112

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18802937 [patent_doc_number] => 11836094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Cryptographic data objects page conversion [patent_app_type] => utility [patent_app_number] => 17/699593 [patent_app_country] => US [patent_app_date] => 2022-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 12564 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699593
Cryptographic data objects page conversion Mar 20, 2022 Issued
Array ( [id] => 18651672 [patent_doc_number] => 20230297508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => APPARATUS AND METHOD FOR HARDWARE-ACCELERATED TEXTURE LOOKUP AND INTERPOLATION [patent_app_type] => utility [patent_app_number] => 17/699067 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 79474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/699067
APPARATUS AND METHOD FOR HARDWARE-ACCELERATED TEXTURE LOOKUP AND INTERPOLATION Mar 17, 2022 Pending
Array ( [id] => 18239244 [patent_doc_number] => 20230071555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => MEMORY SYSTEM FOR DATA ENCRYPTION [patent_app_type] => utility [patent_app_number] => 17/653567 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 518 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17653567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/653567
Memory system for data encryption Mar 3, 2022 Issued
Array ( [id] => 17674873 [patent_doc_number] => 20220188040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => ADJUSTING SCAN EVENT THRESHOLDS TO MITIGATE MEMORY ERRORS [patent_app_type] => utility [patent_app_number] => 17/685102 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685102
Adjusting scan event thresholds to mitigate memory errors Mar 1, 2022 Issued
Array ( [id] => 18225609 [patent_doc_number] => 20230064603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES [patent_app_type] => utility [patent_app_number] => 17/675785 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/675785
SYSTEM AND METHODS FOR INVALIDATING TRANSLATION INFORMATION IN CACHES Feb 17, 2022 Abandoned
Array ( [id] => 18687087 [patent_doc_number] => 11782824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Universal data path architecture for different data array [patent_app_type] => utility [patent_app_number] => 17/667384 [patent_app_country] => US [patent_app_date] => 2022-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667384 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/667384
Universal data path architecture for different data array Feb 7, 2022 Issued
Array ( [id] => 18330794 [patent_doc_number] => 11636036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Unified memory management for a multiple processor system [patent_app_type] => utility [patent_app_number] => 17/587102 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/587102
Unified memory management for a multiple processor system Jan 27, 2022 Issued
Array ( [id] => 18342881 [patent_doc_number] => 11640360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-02 [patent_title] => Processing pipeline where fast data passes slow data [patent_app_type] => utility [patent_app_number] => 17/584001 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7125 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17584001 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/584001
Processing pipeline where fast data passes slow data Jan 24, 2022 Issued
Array ( [id] => 20145690 [patent_doc_number] => 12380033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Refreshing cache regions using a memory controller and multiple tables [patent_app_type] => utility [patent_app_number] => 17/581110 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581110
Refreshing cache regions using a memory controller and multiple tables Jan 20, 2022 Issued
Array ( [id] => 18531865 [patent_doc_number] => 20230236937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => COORDINATED CYCLING CYBER PROTECTION MANAGERS AND REPOSITORIES [patent_app_type] => utility [patent_app_number] => 17/648597 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648597
COORDINATED CYCLING CYBER PROTECTION MANAGERS AND REPOSITORIES Jan 20, 2022 Pending
Array ( [id] => 18513372 [patent_doc_number] => 20230229602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => TRUST DOMAINS FOR PERIPHERAL DEVICES [patent_app_type] => utility [patent_app_number] => 17/577584 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577584 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577584
Trust domains for peripheral devices Jan 17, 2022 Issued
Array ( [id] => 17565058 [patent_doc_number] => 20220129207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => MEMORY SYSTEM AND METHOD FOR CONTROLLING NONVOLATILE MEMORY WITH A HOST MEMORY BUFFER [patent_app_type] => utility [patent_app_number] => 17/572713 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572713 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572713
Memory system and method for controlling nonvolatile memory with a host memory buffer Jan 10, 2022 Issued
Array ( [id] => 18499320 [patent_doc_number] => 20230222070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => REINFORCING HIGH AVAILABILITY OF DISTRIBUTED RELATIONAL DATABASES [patent_app_type] => utility [patent_app_number] => 17/572841 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17572841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/572841
Reinforcing high availability of distributed relational databases Jan 10, 2022 Issued
Array ( [id] => 18234910 [patent_doc_number] => 11599469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-07 [patent_title] => System and methods for cache coherent system using ownership-based scheme [patent_app_type] => utility [patent_app_number] => 17/571004 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9444 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571004
System and methods for cache coherent system using ownership-based scheme Jan 6, 2022 Issued
Array ( [id] => 18471408 [patent_doc_number] => 20230205694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => HYBRID CACHE FOR AUTONOMOUS VEHICLE INFRASTRUCTURE [patent_app_type] => utility [patent_app_number] => 17/561316 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561316 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/561316
Hybrid cache for autonomous vehicle infrastructure Dec 22, 2021 Issued
Array ( [id] => 17535477 [patent_doc_number] => 20220114086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => TECHNIQUES TO EXPAND SYSTEM MEMORY VIA USE OF AVAILABLE DEVICE MEMORY [patent_app_type] => utility [patent_app_number] => 17/560007 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560007
TECHNIQUES TO EXPAND SYSTEM MEMORY VIA USE OF AVAILABLE DEVICE MEMORY Dec 21, 2021 Abandoned
Array ( [id] => 19506519 [patent_doc_number] => 12117939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Stochastic optimization of surface cacheability in parallel processing units [patent_app_type] => utility [patent_app_number] => 17/557475 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557475 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557475
Stochastic optimization of surface cacheability in parallel processing units Dec 20, 2021 Issued
Array ( [id] => 18911799 [patent_doc_number] => 11874777 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Secure communication of virtual machine encrypted memory [patent_app_type] => utility [patent_app_number] => 17/644651 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644651
Secure communication of virtual machine encrypted memory Dec 15, 2021 Issued
Array ( [id] => 18839256 [patent_doc_number] => 11847330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Adjustment of storage device parameters based on workload characteristics [patent_app_type] => utility [patent_app_number] => 17/643789 [patent_app_country] => US [patent_app_date] => 2021-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7202 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643789 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643789
Adjustment of storage device parameters based on workload characteristics Dec 9, 2021 Issued
Array ( [id] => 18855621 [patent_doc_number] => 11853199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Multi-peripheral and/or multi-function export [patent_app_type] => utility [patent_app_number] => 17/538662 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 11331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538662 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538662
Multi-peripheral and/or multi-function export Nov 29, 2021 Issued
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