
Ashokkumar B. Patel
Supervisory Patent Examiner (ID: 18635, Phone: (571)272-3972 , Office: P/2491 )
| Most Active Art Unit | 2154 |
| Art Unit(s) | 2456, 2154, 2491, 2449 |
| Total Applications | 276 |
| Issued Applications | 121 |
| Pending Applications | 21 |
| Abandoned Applications | 133 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 690379
[patent_doc_number] => 07074632
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-11
[patent_title] => 'Miniature optical element for wireless bonding in an electronic instrument'
[patent_app_type] => utility
[patent_app_number] => 10/759266
[patent_app_country] => US
[patent_app_date] => 2004-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 34
[patent_no_of_words] => 9531
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/074/07074632.pdf
[firstpage_image] =>[orig_patent_app_number] => 10759266
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/759266 | Miniature optical element for wireless bonding in an electronic instrument | Jan 19, 2004 | Issued |
Array
(
[id] => 7260076
[patent_doc_number] => 20040150027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'FERROELECTRIC MEMORY DEVICES'
[patent_app_type] => new
[patent_app_number] => 10/758164
[patent_app_country] => US
[patent_app_date] => 2004-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2483
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0150/20040150027.pdf
[firstpage_image] =>[orig_patent_app_number] => 10758164
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/758164 | Ferroelectric memory devices | Jan 15, 2004 | Issued |
Array
(
[id] => 7191440
[patent_doc_number] => 20050040492
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Capacitors of semiconductor devices and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/758346
[patent_app_country] => US
[patent_app_date] => 2004-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1804
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0040/20050040492.pdf
[firstpage_image] =>[orig_patent_app_number] => 10758346
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/758346 | Capacitors of semiconductor devices and methods of fabricating the same | Jan 14, 2004 | Issued |
Array
(
[id] => 7304815
[patent_doc_number] => 20040140472
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-22
[patent_title] => 'Light emitting device'
[patent_app_type] => new
[patent_app_number] => 10/752815
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11885
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0140/20040140472.pdf
[firstpage_image] =>[orig_patent_app_number] => 10752815
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/752815 | Light emitting device | Jan 7, 2004 | Issued |
Array
(
[id] => 7605460
[patent_doc_number] => 07115469
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-03
[patent_title] => 'Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process'
[patent_app_type] => utility
[patent_app_number] => 10/754948
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 6570
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/115/07115469.pdf
[firstpage_image] =>[orig_patent_app_number] => 10754948
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/754948 | Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process | Jan 7, 2004 | Issued |
Array
(
[id] => 6981068
[patent_doc_number] => 20050151136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Light emitting diode having conductive substrate and transparent emitting surface'
[patent_app_type] => utility
[patent_app_number] => 10/754366
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4362
[patent_no_of_claims] => 53
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20050151136.pdf
[firstpage_image] =>[orig_patent_app_number] => 10754366
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/754366 | Light emitting diode having conductive substrate and transparent emitting surface | Jan 7, 2004 | Abandoned |
Array
(
[id] => 6981145
[patent_doc_number] => 20050151213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'METHOD AND STRUCTURE FOR INTEGRATING THERMISTOR'
[patent_app_type] => utility
[patent_app_number] => 10/707746
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 3959
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20050151213.pdf
[firstpage_image] =>[orig_patent_app_number] => 10707746
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/707746 | Method for integrating thermistor | Jan 7, 2004 | Issued |
Array
(
[id] => 694995
[patent_doc_number] => 07071102
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-04
[patent_title] => 'Method of forming a metal silicide layer on non-planar-topography polysilicon'
[patent_app_type] => utility
[patent_app_number] => 10/752276
[patent_app_country] => US
[patent_app_date] => 2004-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5443
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/071/07071102.pdf
[firstpage_image] =>[orig_patent_app_number] => 10752276
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/752276 | Method of forming a metal silicide layer on non-planar-topography polysilicon | Jan 5, 2004 | Issued |
Array
(
[id] => 7148075
[patent_doc_number] => 20050023709
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Alignment mark and alignment method using the same for photolithography to eliminating process bias error'
[patent_app_type] => utility
[patent_app_number] => 10/750805
[patent_app_country] => US
[patent_app_date] => 2004-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2745
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20050023709.pdf
[firstpage_image] =>[orig_patent_app_number] => 10750805
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/750805 | Alignment mark and alignment method using the same for photolithography to eliminating process bias error | Jan 1, 2004 | Issued |
Array
(
[id] => 7309207
[patent_doc_number] => 20040142514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-22
[patent_title] => 'Methods of manufacturing semiconductor devices'
[patent_app_type] => new
[patent_app_number] => 10/746805
[patent_app_country] => US
[patent_app_date] => 2003-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2736
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20040142514.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746805
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746805 | Methods of manufacturing semiconductor devices | Dec 25, 2003 | Issued |
Array
(
[id] => 7442351
[patent_doc_number] => 20040185595
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Method for fabricating complementary metal oxide semiconductor image sensor'
[patent_app_type] => new
[patent_app_number] => 10/746106
[patent_app_country] => US
[patent_app_date] => 2003-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2246
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20040185595.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746106
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746106 | Method for fabricating complementary metal oxide semiconductor image sensor | Dec 23, 2003 | Issued |
Array
(
[id] => 728239
[patent_doc_number] => 07041518
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-09
[patent_title] => 'Low-temperature formation method for emitter tip including copper oxide nanowire or copper nanowire and display device or light source having emitter tip manufactured using the same'
[patent_app_type] => utility
[patent_app_number] => 10/746358
[patent_app_country] => US
[patent_app_date] => 2003-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 4798
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/041/07041518.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746358
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746358 | Low-temperature formation method for emitter tip including copper oxide nanowire or copper nanowire and display device or light source having emitter tip manufactured using the same | Dec 23, 2003 | Issued |
Array
(
[id] => 963610
[patent_doc_number] => 06949422
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-27
[patent_title] => 'Method of crystalizing amorphous silicon for use in thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 10/746019
[patent_app_country] => US
[patent_app_date] => 2003-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 6154
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/949/06949422.pdf
[firstpage_image] =>[orig_patent_app_number] => 10746019
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/746019 | Method of crystalizing amorphous silicon for use in thin film transistor | Dec 22, 2003 | Issued |
Array
(
[id] => 7287361
[patent_doc_number] => 20040147134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Method for manufacturing semiconductor laser optical device'
[patent_app_type] => new
[patent_app_number] => 10/740765
[patent_app_country] => US
[patent_app_date] => 2003-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 11554
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0147/20040147134.pdf
[firstpage_image] =>[orig_patent_app_number] => 10740765
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/740765 | Method for manufacturing semiconductor laser optical device | Dec 21, 2003 | Issued |
Array
(
[id] => 6995079
[patent_doc_number] => 20050134857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Method to monitor silicide formation on product wafers'
[patent_app_type] => utility
[patent_app_number] => 10/742986
[patent_app_country] => US
[patent_app_date] => 2003-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3621
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20050134857.pdf
[firstpage_image] =>[orig_patent_app_number] => 10742986
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/742986 | Method to monitor silicide formation on product wafers | Dec 21, 2003 | Abandoned |
Array
(
[id] => 503485
[patent_doc_number] => 07205672
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-04-17
[patent_title] => 'Flip chip mounted to thermal sensing element through the back side of the chip'
[patent_app_type] => utility
[patent_app_number] => 10/740239
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 2499
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205672.pdf
[firstpage_image] =>[orig_patent_app_number] => 10740239
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/740239 | Flip chip mounted to thermal sensing element through the back side of the chip | Dec 16, 2003 | Issued |
Array
(
[id] => 7328839
[patent_doc_number] => 20040129959
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Semiconductor devices with enlarged recessed gate electrodes and methods of fabrication therefor'
[patent_app_type] => new
[patent_app_number] => 10/738316
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 7647
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0129/20040129959.pdf
[firstpage_image] =>[orig_patent_app_number] => 10738316
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738316 | Semiconductor devices with enlarged recessed gate electrodes | Dec 16, 2003 | Issued |
Array
(
[id] => 517737
[patent_doc_number] => 07189589
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-13
[patent_title] => 'Method of fabrication of a support structure for a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/735695
[patent_app_country] => US
[patent_app_date] => 2003-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 26
[patent_no_of_words] => 3523
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/189/07189589.pdf
[firstpage_image] =>[orig_patent_app_number] => 10735695
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/735695 | Method of fabrication of a support structure for a semiconductor device | Dec 15, 2003 | Issued |
Array
(
[id] => 7448199
[patent_doc_number] => 20040164366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-26
[patent_title] => 'Microelectronic device and method of its manufacture'
[patent_app_type] => new
[patent_app_number] => 10/480606
[patent_app_country] => US
[patent_app_date] => 2003-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3211
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 14
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20040164366.pdf
[firstpage_image] =>[orig_patent_app_number] => 10480606
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/480606 | Microelectronic device and method of its manufacture | Dec 10, 2003 | Abandoned |
Array
(
[id] => 7083383
[patent_doc_number] => 20050048763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Method for preventing contact defects in interlayer dielectric layer'
[patent_app_type] => utility
[patent_app_number] => 10/727966
[patent_app_country] => US
[patent_app_date] => 2003-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1976
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20050048763.pdf
[firstpage_image] =>[orig_patent_app_number] => 10727966
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/727966 | Method for preventing contact defects in interlayer dielectric layer | Dec 3, 2003 | Issued |