Ashokkumar B Patel
Supervisory Patent Examiner (ID: 3931, Phone: (571)272-3972 , Office: P/2491 )
Most Active Art Unit | 2154 |
Art Unit(s) | 2154, 2456, 2491, 2449 |
Total Applications | 276 |
Issued Applications | 121 |
Pending Applications | 21 |
Abandoned Applications | 133 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6456240
[patent_doc_number] => 20020177984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Target simulation system'
[patent_app_type] => new
[patent_app_number] => 10/146851
[patent_app_country] => US
[patent_app_date] => 2002-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1861
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20020177984.pdf
[firstpage_image] =>[orig_patent_app_number] => 10146851
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/146851 | Target simulation system | May 15, 2002 | Abandoned |
Array
(
[id] => 6866090
[patent_doc_number] => 20030191616
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'Simulating program instruction execution and hardware device operation'
[patent_app_type] => new
[patent_app_number] => 10/118427
[patent_app_country] => US
[patent_app_date] => 2002-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4553
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20030191616.pdf
[firstpage_image] =>[orig_patent_app_number] => 10118427
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/118427 | Simulating program instruction execution and hardware device operation | Apr 8, 2002 | Issued |
Array
(
[id] => 6866343
[patent_doc_number] => 20030191869
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'C-API instrumentation for HDL models'
[patent_app_type] => new
[patent_app_number] => 10/116524
[patent_app_country] => US
[patent_app_date] => 2002-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 71
[patent_figures_cnt] => 71
[patent_no_of_words] => 50999
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20030191869.pdf
[firstpage_image] =>[orig_patent_app_number] => 10116524
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/116524 | C-API instrumentation for HDL models | Apr 3, 2002 | Issued |
Array
(
[id] => 694531
[patent_doc_number] => 07076408
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-07-11
[patent_title] => 'Method for ensuring consistent protocol in the location of circuits and connectors having multiple circuit-receiving cavities'
[patent_app_type] => utility
[patent_app_number] => 10/116178
[patent_app_country] => US
[patent_app_date] => 2002-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 3042
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/076/07076408.pdf
[firstpage_image] =>[orig_patent_app_number] => 10116178
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/116178 | Method for ensuring consistent protocol in the location of circuits and connectors having multiple circuit-receiving cavities | Apr 2, 2002 | Issued |
Array
(
[id] => 6728374
[patent_doc_number] => 20030184564
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Method for simulating a celestial sphere in real-time within a data processing system'
[patent_app_type] => new
[patent_app_number] => 10/113242
[patent_app_country] => US
[patent_app_date] => 2002-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2607
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0184/20030184564.pdf
[firstpage_image] =>[orig_patent_app_number] => 10113242
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/113242 | Method for simulating a celestial sphere in real-time within a data processing system | Mar 31, 2002 | Abandoned |
Array
(
[id] => 855773
[patent_doc_number] => 07379860
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-05-27
[patent_title] => 'Method for integrating event-related information and trace information'
[patent_app_type] => utility
[patent_app_number] => 10/112236
[patent_app_country] => US
[patent_app_date] => 2002-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5656
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/379/07379860.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112236
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112236 | Method for integrating event-related information and trace information | Mar 28, 2002 | Issued |
Array
(
[id] => 6731437
[patent_doc_number] => 20030187627
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'I/O velocity projection for bridge attached channel'
[patent_app_type] => new
[patent_app_number] => 10/112800
[patent_app_country] => US
[patent_app_date] => 2002-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 14766
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0187/20030187627.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112800
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112800 | I/O velocity projection for bridge attached channel | Mar 28, 2002 | Issued |
Array
(
[id] => 5909406
[patent_doc_number] => 20020143513
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Simulation with convergence-detection skip-ahead'
[patent_app_type] => new
[patent_app_number] => 10/112179
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5272
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0143/20020143513.pdf
[firstpage_image] =>[orig_patent_app_number] => 10112179
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/112179 | Simulation with convergence-detection skip-ahead | Mar 27, 2002 | Issued |
Array
(
[id] => 477532
[patent_doc_number] => 07231339
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-06-12
[patent_title] => 'Event architecture and method for configuring same'
[patent_app_type] => utility
[patent_app_number] => 10/113586
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 12698
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/231/07231339.pdf
[firstpage_image] =>[orig_patent_app_number] => 10113586
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/113586 | Event architecture and method for configuring same | Mar 27, 2002 | Issued |
Array
(
[id] => 1150119
[patent_doc_number] => 06782518
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'System and method for facilitating coverage feedback testcase generation reproducibility'
[patent_app_type] => B2
[patent_app_number] => 10/109502
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 7093
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/782/06782518.pdf
[firstpage_image] =>[orig_patent_app_number] => 10109502
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/109502 | System and method for facilitating coverage feedback testcase generation reproducibility | Mar 27, 2002 | Issued |
Array
(
[id] => 6732082
[patent_doc_number] => 20030188272
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Synchronous assert module for hardware description language library'
[patent_app_type] => new
[patent_app_number] => 10/107961
[patent_app_country] => US
[patent_app_date] => 2002-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3369
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20030188272.pdf
[firstpage_image] =>[orig_patent_app_number] => 10107961
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/107961 | Synchronous assert module for hardware description language library | Mar 26, 2002 | Abandoned |
Array
(
[id] => 6831041
[patent_doc_number] => 20030182099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Java telematics emulator'
[patent_app_type] => new
[patent_app_number] => 10/104294
[patent_app_country] => US
[patent_app_date] => 2002-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7784
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0182/20030182099.pdf
[firstpage_image] =>[orig_patent_app_number] => 10104294
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/104294 | Java telematics emulator | Mar 21, 2002 | Issued |
Array
(
[id] => 6455882
[patent_doc_number] => 20020177955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-28
[patent_title] => 'Completions architecture'
[patent_app_type] => new
[patent_app_number] => 10/085808
[patent_app_country] => US
[patent_app_date] => 2002-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 12270
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20020177955.pdf
[firstpage_image] =>[orig_patent_app_number] => 10085808
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/085808 | Completions architecture | Feb 27, 2002 | Abandoned |
Array
(
[id] => 6419965
[patent_doc_number] => 20020184001
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-05
[patent_title] => 'System for integrating an emulator and a processor'
[patent_app_type] => new
[patent_app_number] => 10/079552
[patent_app_country] => US
[patent_app_date] => 2002-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2361
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0184/20020184001.pdf
[firstpage_image] =>[orig_patent_app_number] => 10079552
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/079552 | System for integrating an emulator and a processor | Feb 21, 2002 | Abandoned |
Array
(
[id] => 700487
[patent_doc_number] => 07072814
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-07-04
[patent_title] => 'Evolutionary technique for automated synthesis of electronic circuits'
[patent_app_type] => utility
[patent_app_number] => 10/061066
[patent_app_country] => US
[patent_app_date] => 2002-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 7661
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 23
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/072/07072814.pdf
[firstpage_image] =>[orig_patent_app_number] => 10061066
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/061066 | Evolutionary technique for automated synthesis of electronic circuits | Jan 28, 2002 | Issued |
Array
(
[id] => 6134299
[patent_doc_number] => 20020078429
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Design method for control system, control system, adjustment method for control system, exposure method, and exposure apparatus'
[patent_app_type] => new
[patent_app_number] => 09/994827
[patent_app_country] => US
[patent_app_date] => 2001-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 14438
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0078/20020078429.pdf
[firstpage_image] =>[orig_patent_app_number] => 09994827
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/994827 | Design method for control system, control system, adjustment method for control system, exposure method, and exposure apparatus | Nov 27, 2001 | Abandoned |
Array
(
[id] => 6014165
[patent_doc_number] => 20020101824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-01
[patent_title] => 'System and method for connecting a logic circuit simulation to a network'
[patent_app_type] => new
[patent_app_number] => 10/044217
[patent_app_country] => US
[patent_app_date] => 2001-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4582
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20020101824.pdf
[firstpage_image] =>[orig_patent_app_number] => 10044217
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/044217 | System and method for connecting a logic circuit simulation to a network | Nov 18, 2001 | Issued |
Array
(
[id] => 531834
[patent_doc_number] => 07194394
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-20
[patent_title] => 'Method and apparatus for detecting and correcting inaccuracies in curve-fitted models'
[patent_app_type] => utility
[patent_app_number] => 09/999141
[patent_app_country] => US
[patent_app_date] => 2001-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3634
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 12
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/194/07194394.pdf
[firstpage_image] =>[orig_patent_app_number] => 09999141
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/999141 | Method and apparatus for detecting and correcting inaccuracies in curve-fitted models | Nov 14, 2001 | Issued |
Array
(
[id] => 6179914
[patent_doc_number] => 20020156604
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-24
[patent_title] => 'Method for residual form in molecular modeling'
[patent_app_type] => new
[patent_app_number] => 10/053354
[patent_app_country] => US
[patent_app_date] => 2001-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7551
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20020156604.pdf
[firstpage_image] =>[orig_patent_app_number] => 10053354
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/053354 | Method for residual form in molecular modeling | Nov 1, 2001 | Abandoned |
Array
(
[id] => 6673001
[patent_doc_number] => 20030058604
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-27
[patent_title] => 'Method and apparatus to emulate external IO interconnection'
[patent_app_type] => new
[patent_app_number] => 09/982242
[patent_app_country] => US
[patent_app_date] => 2001-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1888
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0058/20030058604.pdf
[firstpage_image] =>[orig_patent_app_number] => 09982242
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/982242 | Method and apparatus to emulate external IO interconnection | Oct 15, 2001 | Abandoned |