Search

Asok K. Sarkar

Examiner (ID: 5343, Phone: (571)272-1970 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2829, 2891, 2813
Total Applications
2309
Issued Applications
2017
Pending Applications
106
Abandoned Applications
207

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18821031 [patent_doc_number] => 20230395372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => METHOD AND SYSTEM FOR FORMING PATTERNED STRUCTURES USING MULTIPLE PATTERNING PROCESS [patent_app_type] => utility [patent_app_number] => 18/236654 [patent_app_country] => US [patent_app_date] => 2023-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236654 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/236654
METHOD AND SYSTEM FOR FORMING PATTERNED STRUCTURES USING MULTIPLE PATTERNING PROCESS Aug 21, 2023 Pending
Array ( [id] => 20792955 [patent_doc_number] => 12666888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Deposition of thick layers of silicon dioxide [patent_app_type] => utility [patent_app_number] => 18/232313 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1802 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/232313
Deposition of thick layers of silicon dioxide Aug 8, 2023 Issued
Array ( [id] => 19773323 [patent_doc_number] => 20250054749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => RF PULSING ASSISTED LOW-K FILM DEPOSITION WITH HIGH MECHANICAL STRENGTH [patent_app_type] => utility [patent_app_number] => 18/366395 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366395 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366395
RF PULSING ASSISTED LOW-K FILM DEPOSITION WITH HIGH MECHANICAL STRENGTH Aug 6, 2023 Pending
Array ( [id] => 19758036 [patent_doc_number] => 20250046601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => CONCURRENT OR CYCLICAL ETCH AND DIRECTIONAL DEPOSITION [patent_app_type] => utility [patent_app_number] => 18/229544 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/229544
Concurrent or cyclical etch and directional deposition Aug 1, 2023 Issued
Array ( [id] => 20933196 [patent_doc_number] => 12727406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-01 [patent_title] => Method of manufacturing integrated circuit device [patent_app_type] => utility [patent_app_number] => 18/228220 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 13062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228220 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228220
METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE Jul 30, 2023 Pending
Array ( [id] => 18958871 [patent_doc_number] => 20240047198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => METHOD OF FORMING TREATED SILICON-CARBON MATERIAL [patent_app_type] => utility [patent_app_number] => 18/227016 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227016 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227016
Method of forming treated silicon-carbon material Jul 26, 2023 Issued
Array ( [id] => 18774212 [patent_doc_number] => 20230369043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/357300 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357300
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium Jul 23, 2023 Issued
Array ( [id] => 18757744 [patent_doc_number] => 20230361207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/223543 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223543 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223543
High electron mobility transistor and method for fabricating the same Jul 17, 2023 Issued
Array ( [id] => 18757442 [patent_doc_number] => 20230360904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/354238 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354238
METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM Jul 17, 2023 Pending
Array ( [id] => 19712562 [patent_doc_number] => 20250022704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => DIRECTIONAL SELECTIVE FILL OF SILICON OXIDE MATERIALS [patent_app_type] => utility [patent_app_number] => 18/221240 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221240 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221240
DIRECTIONAL SELECTIVE FILL OF SILICON OXIDE MATERIALS Jul 11, 2023 Pending
Array ( [id] => 18743361 [patent_doc_number] => 20230352349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SYSTEMS AND METHODS FOR ANALYZING DEFECTS IN CVD FILMS [patent_app_type] => utility [patent_app_number] => 18/349930 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8794 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349930 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349930
Systems and methods for analyzing defects in CVD films Jul 9, 2023 Issued
Array ( [id] => 20404381 [patent_doc_number] => 12494361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Method for selective deposition of silicon nitride and structure including selectively-deposited silicon nitride layer [patent_app_type] => utility [patent_app_number] => 18/218726 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218726
Method for selective deposition of silicon nitride and structure including selectively-deposited silicon nitride layer Jul 5, 2023 Issued
Array ( [id] => 20792957 [patent_doc_number] => 12666890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Method of depositing condensable material onto a surface of a substrate [patent_app_type] => utility [patent_app_number] => 18/218221 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218221 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/218221
Method of depositing condensable material onto a surface of a substrate Jul 4, 2023 Issued
Array ( [id] => 18729284 [patent_doc_number] => 20230343580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/344181 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344181 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344181
Method of processing substrate, method of manufacturing semiconductor device, substrate processing apparatus, and recording medium Jun 28, 2023 Issued
Array ( [id] => 19487234 [patent_doc_number] => 12106958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Method of using dual frequency RF power in a process chamber [patent_app_type] => utility [patent_app_number] => 18/342296 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342296 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342296
Method of using dual frequency RF power in a process chamber Jun 26, 2023 Issued
Array ( [id] => 19842838 [patent_doc_number] => 12255240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Topology selective and sacrificial silicon nitride layer for generating spacers for a semiconductor device drain [patent_app_type] => utility [patent_app_number] => 18/342048 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342048 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342048
Topology selective and sacrificial silicon nitride layer for generating spacers for a semiconductor device drain Jun 26, 2023 Issued
Array ( [id] => 20831443 [patent_doc_number] => 12685046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Doped silicon oxide for bottom-up deposition [patent_app_type] => utility [patent_app_number] => 18/210522 [patent_app_country] => US [patent_app_date] => 2023-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18210522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/210522
Doped silicon oxide for bottom-up deposition Jun 14, 2023 Issued
Array ( [id] => 20756957 [patent_doc_number] => 12649716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-09 [patent_title] => Silicon compound and method of manufacturing integrated circuit device using the same [patent_app_type] => utility [patent_app_number] => 18/209583 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209583
Silicon compound and method of manufacturing integrated circuit device using the same Jun 13, 2023 Issued
Array ( [id] => 18848743 [patent_doc_number] => 20230411147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => METHODS AND SYSTEMS FOR FORMING A LAYER COMPRISING SILICON OXIDE [patent_app_type] => utility [patent_app_number] => 18/334058 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334058
Methods and systems for forming a layer comprising silicon oxide Jun 12, 2023 Issued
Array ( [id] => 20229252 [patent_doc_number] => 12417907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Method for increasing bridging process window of contact hole and gate of device [patent_app_type] => utility [patent_app_number] => 18/201453 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201453 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201453
Method for increasing bridging process window of contact hole and gate of device May 23, 2023 Issued
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