Search

Asok K. Sarkar

Examiner (ID: 5343, Phone: (571)272-1970 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2829, 2891, 2813
Total Applications
2309
Issued Applications
2017
Pending Applications
106
Abandoned Applications
207

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10590525 [patent_doc_number] => 09312145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Conformal nitridation of one or more fin-type transistor layers' [patent_app_type] => utility [patent_app_number] => 14/200197 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7652 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200197 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200197
Conformal nitridation of one or more fin-type transistor layers Mar 6, 2014 Issued
Array ( [id] => 10370344 [patent_doc_number] => 20150255349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'APPROACHES FOR CLEANING A WAFER DURING HYBRID LASER SCRIBING AND PLASMA ETCHING WAFER DICING PROCESSES' [patent_app_type] => utility [patent_app_number] => 14/201452 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11134 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14201452 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/201452
APPROACHES FOR CLEANING A WAFER DURING HYBRID LASER SCRIBING AND PLASMA ETCHING WAFER DICING PROCESSES Mar 6, 2014 Abandoned
Array ( [id] => 10511004 [patent_doc_number] => 09238578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-19 [patent_title] => 'Semiconductor arrangement with stress release and thermal insulation' [patent_app_type] => utility [patent_app_number] => 14/200101 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200101 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200101
Semiconductor arrangement with stress release and thermal insulation Mar 6, 2014 Issued
Array ( [id] => 10138613 [patent_doc_number] => 09171935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'FinFET formation with late fin reveal' [patent_app_type] => utility [patent_app_number] => 14/200104 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 8673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200104 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200104
FinFET formation with late fin reveal Mar 6, 2014 Issued
Array ( [id] => 10165478 [patent_doc_number] => 09196711 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Fin field effect transistor including self-aligned raised active regions' [patent_app_type] => utility [patent_app_number] => 14/200851 [patent_app_country] => US [patent_app_date] => 2014-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 46 [patent_no_of_words] => 7043 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14200851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/200851
Fin field effect transistor including self-aligned raised active regions Mar 6, 2014 Issued
Array ( [id] => 10086301 [patent_doc_number] => 09123655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Methods of forming layer patterns of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/190797 [patent_app_country] => US [patent_app_date] => 2014-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6744 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190797 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190797
Methods of forming layer patterns of a semiconductor device Feb 25, 2014 Issued
Array ( [id] => 9756891 [patent_doc_number] => 20140287592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'METHODS OF FORMING A LAYER' [patent_app_type] => utility [patent_app_number] => 14/189367 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189367 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189367
Methods of forming a layer Feb 24, 2014 Issued
Array ( [id] => 10954056 [patent_doc_number] => 20140357077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES' [patent_app_type] => utility [patent_app_number] => 14/190090 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5818 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190090 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190090
METHODS FOR FABRICATING SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES Feb 24, 2014 Abandoned
Array ( [id] => 9699039 [patent_doc_number] => 20140248724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGES' [patent_app_type] => utility [patent_app_number] => 14/190057 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 3935 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14190057 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/190057
METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGES Feb 24, 2014 Abandoned
Array ( [id] => 9944141 [patent_doc_number] => 08993441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Methods of forming a thin layer and methods of manufacturing a phase change memory device using the same' [patent_app_type] => utility [patent_app_number] => 14/189053 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 7424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189053 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/189053
Methods of forming a thin layer and methods of manufacturing a phase change memory device using the same Feb 24, 2014 Issued
Array ( [id] => 10080023 [patent_doc_number] => 09117880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/188378 [patent_app_country] => US [patent_app_date] => 2014-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5224 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14188378 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/188378
Method for manufacturing semiconductor device Feb 23, 2014 Issued
Array ( [id] => 11776260 [patent_doc_number] => 09385215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'V-shaped SiGe recess volume trim for improved device performance and layout dependence' [patent_app_type] => utility [patent_app_number] => 14/182777 [patent_app_country] => US [patent_app_date] => 2014-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14182777 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/182777
V-shaped SiGe recess volume trim for improved device performance and layout dependence Feb 17, 2014 Issued
Array ( [id] => 9515262 [patent_doc_number] => 20140151754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SOLID-STATE IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/176347 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 17013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176347 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/176347
SOLID-STATE IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING SAME Feb 9, 2014 Abandoned
Array ( [id] => 10570283 [patent_doc_number] => 09293462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Integrated circuits with dual silicide contacts and methods for fabricating same' [patent_app_type] => utility [patent_app_number] => 14/167778 [patent_app_country] => US [patent_app_date] => 2014-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 4316 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14167778 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/167778
Integrated circuits with dual silicide contacts and methods for fabricating same Jan 28, 2014 Issued
Array ( [id] => 9642605 [patent_doc_number] => 20140220717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/162754 [patent_app_country] => US [patent_app_date] => 2014-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14162754 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/162754
METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE Jan 23, 2014 Abandoned
Array ( [id] => 10321787 [patent_doc_number] => 20150206791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/161247 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14161247 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/161247
Method for forming semiconductor device structure Jan 21, 2014 Issued
Array ( [id] => 9989530 [patent_doc_number] => 09034733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'Semiconductor die singulation method' [patent_app_type] => utility [patent_app_number] => 14/159648 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 4969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14159648 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/159648
Semiconductor die singulation method Jan 20, 2014 Issued
Array ( [id] => 10317865 [patent_doc_number] => 20150202868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'SUBTRACTIVE THREE DIMENSIONAL FABRICATION OF AN INKJET PLATE' [patent_app_type] => utility [patent_app_number] => 14/160358 [patent_app_country] => US [patent_app_date] => 2014-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1659 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160358 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/160358
Subtractive three dimensional fabrication of an inkjet plate Jan 20, 2014 Issued
Array ( [id] => 10322501 [patent_doc_number] => 20150207505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING ENHANCED VARIABILITY' [patent_app_type] => utility [patent_app_number] => 14/158917 [patent_app_country] => US [patent_app_date] => 2014-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158917 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158917
Semiconductor device including enhanced variability Jan 19, 2014 Issued
Array ( [id] => 10321869 [patent_doc_number] => 20150206873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'Alignment Marks in Non-STI Isolation Formation and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/157720 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3445 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157720 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/157720
Alignment marks in non-STI isolation formation and methods of forming the same Jan 16, 2014 Issued
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