
Asok K. Sarkar
Examiner (ID: 5343, Phone: (571)272-1970 , Office: P/2891 )
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2829, 2891, 2813 |
| Total Applications | 2309 |
| Issued Applications | 2017 |
| Pending Applications | 106 |
| Abandoned Applications | 207 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9051382
[patent_doc_number] => 20130249096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'THROUGH SILICON VIA FILLING'
[patent_app_type] => utility
[patent_app_number] => 13/591026
[patent_app_country] => US
[patent_app_date] => 2012-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5706
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13591026
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/591026 | THROUGH SILICON VIA FILLING | Aug 20, 2012 | Abandoned |
Array
(
[id] => 9327966
[patent_doc_number] => 20140054748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-27
[patent_title] => 'EDGE TRIMMING METHOD FOR SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER HAVING TRIMMED EDGE'
[patent_app_type] => utility
[patent_app_number] => 13/590196
[patent_app_country] => US
[patent_app_date] => 2012-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2875
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590196
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/590196 | EDGE TRIMMING METHOD FOR SEMICONDUCTOR WAFER AND SEMICONDUCTOR WAFER HAVING TRIMMED EDGE | Aug 20, 2012 | Abandoned |
Array
(
[id] => 8694784
[patent_doc_number] => 20130056793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-07
[patent_title] => 'PROVIDING GROUP V AND GROUP VI OVER PRESSURE FOR THERMAL TREATMENT OF COMPOUND SEMICONDUCTOR THIN FILMS'
[patent_app_type] => utility
[patent_app_number] => 13/589355
[patent_app_country] => US
[patent_app_date] => 2012-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 6437
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589355
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/589355 | PROVIDING GROUP V AND GROUP VI OVER PRESSURE FOR THERMAL TREATMENT OF COMPOUND SEMICONDUCTOR THIN FILMS | Aug 19, 2012 | Abandoned |
Array
(
[id] => 9318894
[patent_doc_number] => 20140051232
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-20
[patent_title] => 'SEMICONDUCTOR DIE SINGULATION METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/589985
[patent_app_country] => US
[patent_app_date] => 2012-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4479
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589985
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/589985 | Semiconductor die singulation method | Aug 19, 2012 | Issued |
Array
(
[id] => 8684515
[patent_doc_number] => 20130052799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-28
[patent_title] => 'MANUFACTURING METHOD OF SOI SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/589704
[patent_app_country] => US
[patent_app_date] => 2012-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 22287
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589704
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/589704 | Manufacturing method of SOI substrate | Aug 19, 2012 | Issued |
Array
(
[id] => 8853713
[patent_doc_number] => 20130143388
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-06
[patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/588119
[patent_app_country] => US
[patent_app_date] => 2012-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2075
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13588119
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/588119 | Method for manufacturing semiconductor device | Aug 16, 2012 | Issued |
Array
(
[id] => 9552184
[patent_doc_number] => 08759232
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-24
[patent_title] => 'Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress'
[patent_app_type] => utility
[patent_app_number] => 13/588460
[patent_app_country] => US
[patent_app_date] => 2012-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9205
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 260
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13588460
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/588460 | Compressive stress transfer in an interlayer dielectric of a semiconductor device by providing a bi-layer of superior adhesion and internal stress | Aug 16, 2012 | Issued |
Array
(
[id] => 9316620
[patent_doc_number] => 20140048958
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-20
[patent_title] => 'Pad Sidewall Spacers and Method of Making Pad Sidewall Spacers'
[patent_app_type] => utility
[patent_app_number] => 13/587816
[patent_app_country] => US
[patent_app_date] => 2012-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4696
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13587816
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/587816 | Pad sidewall spacers and method of making pad sidewall spacers | Aug 15, 2012 | Issued |
Array
(
[id] => 9318891
[patent_doc_number] => 20140051229
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-20
[patent_title] => 'SUB-10 NM GRAPHENE NANORIBBON LATTICES'
[patent_app_type] => utility
[patent_app_number] => 13/586527
[patent_app_country] => US
[patent_app_date] => 2012-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8024
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13586527
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/586527 | Sub-10 nm graphene nanoribbon lattices | Aug 14, 2012 | Issued |
Array
(
[id] => 9303718
[patent_doc_number] => 20140042392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'DOUBLE CONTACTS FOR CARBON NANOTUBES THIN FILM DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/585465
[patent_app_country] => US
[patent_app_date] => 2012-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2694
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13585465
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/585465 | Double contacts for carbon nanotubes thin film devices | Aug 13, 2012 | Issued |
Array
(
[id] => 9306647
[patent_doc_number] => 20140045321
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'ACCELERATED FURNACE RAMP RATES FOR REDUCED SLIP'
[patent_app_type] => utility
[patent_app_number] => 13/584004
[patent_app_country] => US
[patent_app_date] => 2012-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2579
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13584004
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/584004 | Accelerated furnace ramp rates for reduced slip | Aug 12, 2012 | Issued |
Array
(
[id] => 9306659
[patent_doc_number] => 20140045333
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-13
[patent_title] => 'DOUBLE CONTACTS FOR CARBON NANOTUBES THIN FILM DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/571607
[patent_app_country] => US
[patent_app_date] => 2012-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2650
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13571607
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/571607 | Double contacts for carbon nanotubes thin film devices | Aug 9, 2012 | Issued |
Array
(
[id] => 8944021
[patent_doc_number] => 08497199
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-07-30
[patent_title] => 'Method for fabricating a thin film formed with a uniform single-size monolayer of spherical AZO nanoparticles'
[patent_app_type] => utility
[patent_app_number] => 13/569371
[patent_app_country] => US
[patent_app_date] => 2012-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3163
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 266
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13569371
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/569371 | Method for fabricating a thin film formed with a uniform single-size monolayer of spherical AZO nanoparticles | Aug 7, 2012 | Issued |
Array
(
[id] => 10857448
[patent_doc_number] => 08883646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-11-11
[patent_title] => 'Self-assembled monolayer for pattern formation'
[patent_app_type] => utility
[patent_app_number] => 13/567250
[patent_app_country] => US
[patent_app_date] => 2012-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 3426
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13567250
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/567250 | Self-assembled monolayer for pattern formation | Aug 5, 2012 | Issued |
Array
(
[id] => 8496041
[patent_doc_number] => 20120295449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-22
[patent_title] => 'Method of Depositing Dielectric Film by ALD Using Precursor Containing Silicon, Hydrocarbon, and Halogen'
[patent_app_type] => utility
[patent_app_number] => 13/566069
[patent_app_country] => US
[patent_app_date] => 2012-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8220
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13566069
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/566069 | Method of depositing dielectric film by ALD using precursor containing silicon, hydrocarbon, and halogen | Aug 2, 2012 | Issued |
Array
(
[id] => 8649235
[patent_doc_number] => 20130034965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-07
[patent_title] => 'METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES'
[patent_app_type] => utility
[patent_app_number] => 13/564611
[patent_app_country] => US
[patent_app_date] => 2012-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 10228
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564611
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/564611 | METHODS OF FORMING FINE PATTERNS USING DRY ETCH-BACK PROCESSES | Jul 31, 2012 | Abandoned |
Array
(
[id] => 9294759
[patent_doc_number] => 20140038393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-02-06
[patent_title] => 'METHOD AND SYSTEM FOR ION-ASSISTED PROCESSING'
[patent_app_type] => utility
[patent_app_number] => 13/563056
[patent_app_country] => US
[patent_app_date] => 2012-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7261
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563056
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/563056 | Method and system for ion-assisted processing | Jul 30, 2012 | Issued |
Array
(
[id] => 8671051
[patent_doc_number] => 20130045589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-21
[patent_title] => 'SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/562826
[patent_app_country] => US
[patent_app_date] => 2012-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 29
[patent_no_of_words] => 16807
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562826
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/562826 | Semiconductor devices and methods of manufacturing the same | Jul 30, 2012 | Issued |
Array
(
[id] => 9286135
[patent_doc_number] => 08642464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-04
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/562818
[patent_app_country] => US
[patent_app_date] => 2012-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 72
[patent_no_of_words] => 5344
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13562818
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/562818 | Method of manufacturing semiconductor device | Jul 30, 2012 | Issued |
Array
(
[id] => 8814714
[patent_doc_number] => 20130115759
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-09
[patent_title] => 'Methods of Fabricating Semiconductor Devices'
[patent_app_type] => utility
[patent_app_number] => 13/561245
[patent_app_country] => US
[patent_app_date] => 2012-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 8108
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561245
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/561245 | Methods of fabricating semiconductor devices | Jul 29, 2012 | Issued |