
Asok K. Sarkar
Examiner (ID: 5343, Phone: (571)272-1970 , Office: P/2891 )
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2829, 2891, 2813 |
| Total Applications | 2309 |
| Issued Applications | 2017 |
| Pending Applications | 106 |
| Abandoned Applications | 207 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10888092
[patent_doc_number] => 08912088
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-16
[patent_title] => 'Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate'
[patent_app_type] => utility
[patent_app_number] => 13/879803
[patent_app_country] => US
[patent_app_date] => 2011-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 6375
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13879803
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/879803 | Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate | Nov 17, 2011 | Issued |
Array
(
[id] => 8920908
[patent_doc_number] => 08486840
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-16
[patent_title] => 'Inverse spacer processing'
[patent_app_type] => utility
[patent_app_number] => 13/294340
[patent_app_country] => US
[patent_app_date] => 2011-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 3880
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13294340
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/294340 | Inverse spacer processing | Nov 10, 2011 | Issued |
Array
(
[id] => 8796986
[patent_doc_number] => 08435854
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-05-07
[patent_title] => 'Top electrode templating for DRAM capacitor'
[patent_app_type] => utility
[patent_app_number] => 13/294309
[patent_app_country] => US
[patent_app_date] => 2011-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5760
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13294309
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/294309 | Top electrode templating for DRAM capacitor | Nov 10, 2011 | Issued |
Array
(
[id] => 8198592
[patent_doc_number] => 20120122307
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-17
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 13/294169
[patent_app_country] => US
[patent_app_date] => 2011-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5136
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20120122307.pdf
[firstpage_image] =>[orig_patent_app_number] => 13294169
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/294169 | Method of manufacturing semiconductor devices | Nov 9, 2011 | Issued |
Array
(
[id] => 8265363
[patent_doc_number] => 20120164791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-28
[patent_title] => 'Substrate for semiconductor package and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 13/373292
[patent_app_country] => US
[patent_app_date] => 2011-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3522
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13373292
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/373292 | Substrate for semiconductor package and method for manufacturing the same | Nov 9, 2011 | Abandoned |
Array
(
[id] => 8807738
[patent_doc_number] => 08445390
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-05-21
[patent_title] => 'Patterning of antistiction films for electromechanical systems devices'
[patent_app_type] => utility
[patent_app_number] => 13/294114
[patent_app_country] => US
[patent_app_date] => 2011-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 14179
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13294114
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/294114 | Patterning of antistiction films for electromechanical systems devices | Nov 9, 2011 | Issued |
Array
(
[id] => 8875724
[patent_doc_number] => 08470689
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-25
[patent_title] => 'Method for forming a multilayer structure'
[patent_app_type] => utility
[patent_app_number] => 13/293652
[patent_app_country] => US
[patent_app_date] => 2011-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 3358
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13293652
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/293652 | Method for forming a multilayer structure | Nov 9, 2011 | Issued |
Array
(
[id] => 9020351
[patent_doc_number] => 08530336
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-10
[patent_title] => 'Method for manufacturing semiconductor substrate'
[patent_app_type] => utility
[patent_app_number] => 13/292190
[patent_app_country] => US
[patent_app_date] => 2011-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 35
[patent_no_of_words] => 10935
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13292190
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/292190 | Method for manufacturing semiconductor substrate | Nov 8, 2011 | Issued |
Array
(
[id] => 8277973
[patent_doc_number] => 20120171844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-07-05
[patent_title] => 'DICING DIE BONDING FILM, SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/287367
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 6386
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287367
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/287367 | Dicing die bonding film, semiconductor wafer, and semiconductor device | Nov 1, 2011 | Issued |
Array
(
[id] => 8807715
[patent_doc_number] => 08445367
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-21
[patent_title] => 'Methods of manufacturing semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 13/287509
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 26
[patent_no_of_words] => 10112
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287509
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/287509 | Methods of manufacturing semiconductor devices | Nov 1, 2011 | Issued |
Array
(
[id] => 8227973
[patent_doc_number] => 20120142179
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-07
[patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/287345
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7823
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287345
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/287345 | Method of manufacturing semiconductor device | Nov 1, 2011 | Issued |
Array
(
[id] => 8172662
[patent_doc_number] => 20120108027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-03
[patent_title] => 'IMPROVED SILICIDE METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/287671
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2967
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20120108027.pdf
[firstpage_image] =>[orig_patent_app_number] => 13287671
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/287671 | Silicide method | Nov 1, 2011 | Issued |
Array
(
[id] => 8172609
[patent_doc_number] => 20120108003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-03
[patent_title] => 'METHOD FOR PRODUCING A SOLAR CELL'
[patent_app_type] => utility
[patent_app_number] => 13/287212
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7566
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20120108003.pdf
[firstpage_image] =>[orig_patent_app_number] => 13287212
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/287212 | METHOD FOR PRODUCING A SOLAR CELL | Nov 1, 2011 | Abandoned |
Array
(
[id] => 8870685
[patent_doc_number] => 08466062
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-18
[patent_title] => 'TSV backside processing using copper damascene interconnect technology'
[patent_app_type] => utility
[patent_app_number] => 13/287220
[patent_app_country] => US
[patent_app_date] => 2011-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 25
[patent_no_of_words] => 10134
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287220
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/287220 | TSV backside processing using copper damascene interconnect technology | Nov 1, 2011 | Issued |
Array
(
[id] => 7773200
[patent_doc_number] => 20120038051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-16
[patent_title] => 'BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/281491
[patent_app_country] => US
[patent_app_date] => 2011-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2662
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20120038051.pdf
[firstpage_image] =>[orig_patent_app_number] => 13281491
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/281491 | Buried silicide local interconnect with sidewall spacers and method for making the same | Oct 25, 2011 | Issued |
Array
(
[id] => 9749696
[patent_doc_number] => 08841170
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-23
[patent_title] => 'Methods for scribing of semiconductor devices with improved sidewall passivation'
[patent_app_type] => utility
[patent_app_number] => 13/879971
[patent_app_country] => US
[patent_app_date] => 2011-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 5598
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13879971
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/879971 | Methods for scribing of semiconductor devices with improved sidewall passivation | Oct 20, 2011 | Issued |
Array
(
[id] => 8629747
[patent_doc_number] => 08361819
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-29
[patent_title] => 'Methods of fabricating a light-emitting device'
[patent_app_type] => utility
[patent_app_number] => 13/317254
[patent_app_country] => US
[patent_app_date] => 2011-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 20
[patent_no_of_words] => 6989
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13317254
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/317254 | Methods of fabricating a light-emitting device | Oct 12, 2011 | Issued |
Array
(
[id] => 8858514
[patent_doc_number] => 08461049
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-11
[patent_title] => 'Method for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 13/270229
[patent_app_country] => US
[patent_app_date] => 2011-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2894
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13270229
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/270229 | Method for fabricating semiconductor device | Oct 10, 2011 | Issued |
Array
(
[id] => 8323984
[patent_doc_number] => 20120196399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-02
[patent_title] => 'Nitrogen Reactive Sputtering of Cu-In-Ga-N For Solar Cells'
[patent_app_type] => utility
[patent_app_number] => 13/269713
[patent_app_country] => US
[patent_app_date] => 2011-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7230
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13269713
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/269713 | Nitrogen reactive sputtering of Cu-In-Ga-N for solar cells | Oct 9, 2011 | Issued |
Array
(
[id] => 8127539
[patent_doc_number] => 20120088318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-04-12
[patent_title] => 'Method for Fabricating a Vertical Light-Emitting Diode with High Brightness'
[patent_app_type] => utility
[patent_app_number] => 13/269658
[patent_app_country] => US
[patent_app_date] => 2011-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2781
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20120088318.pdf
[firstpage_image] =>[orig_patent_app_number] => 13269658
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/269658 | Method for Fabricating a Vertical Light-Emitting Diode with High Brightness | Oct 9, 2011 | Abandoned |