Search

Asok K. Sarkar

Examiner (ID: 5343, Phone: (571)272-1970 , Office: P/2891 )

Most Active Art Unit
2891
Art Unit(s)
2829, 2891, 2813
Total Applications
2309
Issued Applications
2017
Pending Applications
106
Abandoned Applications
207

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7773921 [patent_doc_number] => 08119486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Methods of manufacturing semiconductor devices having a recessed-channel' [patent_app_type] => utility [patent_app_number] => 12/984176 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/119/08119486.pdf [firstpage_image] =>[orig_patent_app_number] => 12984176 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984176
Methods of manufacturing semiconductor devices having a recessed-channel Jan 3, 2011 Issued
Array ( [id] => 7762185 [patent_doc_number] => 08114769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-14 [patent_title] => 'Methods and structures to enable self-aligned via etch for Cu damascene structure using trench first metal hard mask (TFMHM) scheme' [patent_app_type] => utility [patent_app_number] => 12/982956 [patent_app_country] => US [patent_app_date] => 2010-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/114/08114769.pdf [firstpage_image] =>[orig_patent_app_number] => 12982956 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982956
Methods and structures to enable self-aligned via etch for Cu damascene structure using trench first metal hard mask (TFMHM) scheme Dec 30, 2010 Issued
Array ( [id] => 4599497 [patent_doc_number] => 07977208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Method and apparatus for packaging circuit devices' [patent_app_type] => utility [patent_app_number] => 12/982346 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4766 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/977/07977208.pdf [firstpage_image] =>[orig_patent_app_number] => 12982346 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982346
Method and apparatus for packaging circuit devices Dec 29, 2010 Issued
Array ( [id] => 9691648 [patent_doc_number] => 08822241 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/981796 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4927 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981796 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981796
Method of manufacturing a semiconductor device Dec 29, 2010 Issued
Array ( [id] => 7773975 [patent_doc_number] => 08119512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-21 [patent_title] => 'Method for fabricating semiconductor device with damascene bit line' [patent_app_type] => utility [patent_app_number] => 12/980902 [patent_app_country] => US [patent_app_date] => 2010-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/119/08119512.pdf [firstpage_image] =>[orig_patent_app_number] => 12980902 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/980902
Method for fabricating semiconductor device with damascene bit line Dec 28, 2010 Issued
Array ( [id] => 7496798 [patent_doc_number] => 20110260238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURINMG THE SAME' [patent_app_type] => utility [patent_app_number] => 12/979865 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4509 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260238.pdf [firstpage_image] =>[orig_patent_app_number] => 12979865 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979865
Semiconductor device and method for manufacturing the same Dec 27, 2010 Issued
Array ( [id] => 8252520 [patent_doc_number] => 20120156842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/979025 [patent_app_country] => US [patent_app_date] => 2010-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9190 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20120156842.pdf [firstpage_image] =>[orig_patent_app_number] => 12979025 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979025
METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE Dec 26, 2010 Abandoned
Array ( [id] => 6161991 [patent_doc_number] => 20110159697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'ETCHING METHOD AND ETCHING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/977266 [patent_app_country] => US [patent_app_date] => 2010-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4410 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20110159697.pdf [firstpage_image] =>[orig_patent_app_number] => 12977266 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/977266
Etching method and etching apparatus Dec 22, 2010 Issued
Array ( [id] => 7762047 [patent_doc_number] => 08114712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-14 [patent_title] => 'Method for fabricating a semiconductor device package' [patent_app_type] => utility [patent_app_number] => 12/975466 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7429 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/114/08114712.pdf [firstpage_image] =>[orig_patent_app_number] => 12975466 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/975466
Method for fabricating a semiconductor device package Dec 21, 2010 Issued
12/955456 SEMICONDUCTOR DEVICE WITH ANALOG CAPACITOR AND METHOD OF FABRICATING THE SAME Nov 28, 2010 Abandoned
Array ( [id] => 6070770 [patent_doc_number] => 20110045621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'VERTICAL CAVITY SURFACE EMITTING LASER HAVING MULTIPLE TOP-SIDE CONTACTS' [patent_app_type] => utility [patent_app_number] => 12/917449 [patent_app_country] => US [patent_app_date] => 2010-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12205 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20110045621.pdf [firstpage_image] =>[orig_patent_app_number] => 12917449 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/917449
Vertical cavity surface emitting laser having multiple top-side contacts Oct 31, 2010 Issued
Array ( [id] => 6114315 [patent_doc_number] => 20110073908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'III-V Semiconductor Device Structures' [patent_app_type] => utility [patent_app_number] => 12/907787 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20110073908.pdf [firstpage_image] =>[orig_patent_app_number] => 12907787 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/907787
III-V semiconductor device structures Oct 18, 2010 Issued
Array ( [id] => 5948044 [patent_doc_number] => 20110031471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'Laser-Induced Structuring of Substrate Surfaces' [patent_app_type] => utility [patent_app_number] => 12/906508 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6778 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20110031471.pdf [firstpage_image] =>[orig_patent_app_number] => 12906508 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906508
Laser-induced structuring of substrate surfaces Oct 17, 2010 Issued
Array ( [id] => 6135322 [patent_doc_number] => 20110008929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'ALIGNED POLYMERS FOR AN ORGANIC TFT' [patent_app_type] => utility [patent_app_number] => 12/888180 [patent_app_country] => US [patent_app_date] => 2010-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7028 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20110008929.pdf [firstpage_image] =>[orig_patent_app_number] => 12888180 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/888180
Aligned polymers for an organic TFT Sep 21, 2010 Issued
Array ( [id] => 5976921 [patent_doc_number] => 20110070675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'METHOD FOR MANUFACTURING MICROMECHANICAL COMPONENTS' [patent_app_type] => utility [patent_app_number] => 12/884823 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3778 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20110070675.pdf [firstpage_image] =>[orig_patent_app_number] => 12884823 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/884823
Method for manufacturing micromechanical components Sep 16, 2010 Issued
Array ( [id] => 6202444 [patent_doc_number] => 20110065230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'METHOD FOR MANUFACTURING SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 12/869021 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4765 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20110065230.pdf [firstpage_image] =>[orig_patent_app_number] => 12869021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869021
Method for manufacturing solar cell Aug 25, 2010 Issued
Array ( [id] => 6149405 [patent_doc_number] => 20110021000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'METHOD FOR MANUFACTURING RESISTANCE CHANGE ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/852230 [patent_app_country] => US [patent_app_date] => 2010-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3976 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20110021000.pdf [firstpage_image] =>[orig_patent_app_number] => 12852230 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/852230
Method for manufacturing resistance change element Aug 5, 2010 Issued
Array ( [id] => 7748815 [patent_doc_number] => 20120024336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'CHARGE CONTROL OF SOLAR CELL PASSIVATION LAYERS' [patent_app_type] => utility [patent_app_number] => 12/844746 [patent_app_country] => US [patent_app_date] => 2010-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2685 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20120024336.pdf [firstpage_image] =>[orig_patent_app_number] => 12844746 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/844746
CHARGE CONTROL OF SOLAR CELL PASSIVATION LAYERS Jul 26, 2010 Abandoned
Array ( [id] => 7535705 [patent_doc_number] => 08049334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-01 [patent_title] => 'Buried silicide local interconnect with sidewall spacers and method for making the same' [patent_app_type] => utility [patent_app_number] => 12/843131 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2642 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/049/08049334.pdf [firstpage_image] =>[orig_patent_app_number] => 12843131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843131
Buried silicide local interconnect with sidewall spacers and method for making the same Jul 25, 2010 Issued
Array ( [id] => 8146627 [patent_doc_number] => 08163634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Devices with graphene layers' [patent_app_type] => utility [patent_app_number] => 12/838683 [patent_app_country] => US [patent_app_date] => 2010-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3385 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/163/08163634.pdf [firstpage_image] =>[orig_patent_app_number] => 12838683 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/838683
Devices with graphene layers Jul 18, 2010 Issued
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