Search

Aurangzeb Hassan

Examiner (ID: 18198, Phone: (571)272-8625 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2182, 2184
Total Applications
858
Issued Applications
624
Pending Applications
78
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17492187 [patent_doc_number] => 11281490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Dynamic assignment of interrupts based on input/output metrics [patent_app_type] => utility [patent_app_number] => 17/128394 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5636 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128394 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128394
Dynamic assignment of interrupts based on input/output metrics Dec 20, 2020 Issued
Array ( [id] => 16729860 [patent_doc_number] => 20210097007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => ELECTRONIC DEVICE AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/117439 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117439
ELECTRONIC DEVICE AND CONTROL METHOD Dec 9, 2020 Abandoned
Array ( [id] => 18981976 [patent_doc_number] => 11907149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Sideband signaling in universal serial bus (USB) type-C communication links [patent_app_type] => utility [patent_app_number] => 17/116454 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5327 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116454
Sideband signaling in universal serial bus (USB) type-C communication links Dec 8, 2020 Issued
Array ( [id] => 17643992 [patent_doc_number] => 20220171730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => PIN MAPPING FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/108742 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108742 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108742
Pin mapping for memory devices Nov 30, 2020 Issued
Array ( [id] => 17643991 [patent_doc_number] => 20220171729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => SYSTEMS AND METHODS FOR SINGLE-WIRE IN-BAND PULSE-ADDRESSABLE MULTIPLEXER [patent_app_type] => utility [patent_app_number] => 17/106434 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106434
Systems and methods for single-wire in-band pulse-addressable multiplexer Nov 29, 2020 Issued
Array ( [id] => 16690688 [patent_doc_number] => 20210073166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SYSTEM ON CHIP INCLUDING CLOCK MANAGEMENT UNIT AND METHOD OF OPERATING THE SYSTEM ON CHIP [patent_app_type] => utility [patent_app_number] => 16/952681 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952681 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952681
System on chip including clock management unit and method of operating the system on chip Nov 18, 2020 Issued
Array ( [id] => 17786558 [patent_doc_number] => 11409682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Folded memory modules [patent_app_type] => utility [patent_app_number] => 16/950861 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950861 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950861
Folded memory modules Nov 16, 2020 Issued
Array ( [id] => 17715136 [patent_doc_number] => 11379127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Method and system for enhancing a distributed storage system by decoupling computation and network tasks [patent_app_type] => utility [patent_app_number] => 17/087101 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087101 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087101
Method and system for enhancing a distributed storage system by decoupling computation and network tasks Nov 1, 2020 Issued
Array ( [id] => 16623601 [patent_doc_number] => 20210042254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => ACCELERATOR CONTROLLER HUB [patent_app_type] => utility [patent_app_number] => 17/083200 [patent_app_country] => US [patent_app_date] => 2020-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083200
Accelerator controller hub Oct 27, 2020 Issued
Array ( [id] => 19841582 [patent_doc_number] => 12253969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Validation of a time synchronization [patent_app_type] => utility [patent_app_number] => 18/031187 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6062 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18031187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/031187
Validation of a time synchronization Oct 11, 2020 Issued
Array ( [id] => 17499510 [patent_doc_number] => 11288216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-29 [patent_title] => Priority reversing data traffic for latency sensitive peripherals [patent_app_type] => utility [patent_app_number] => 17/039370 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6215 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039370
Priority reversing data traffic for latency sensitive peripherals Sep 29, 2020 Issued
Array ( [id] => 17431792 [patent_doc_number] => 20220059501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SEMICONDUCTOR DEVICE IN 3D STACK WITH COMMUNICATION INTERFACE AND MANAGING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/037753 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037753 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/037753
Semiconductor device in 3D stack with communication interface and managing method thereof Sep 29, 2020 Issued
Array ( [id] => 17507983 [patent_doc_number] => 20220101086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => RECONFIGURABLE HARDWARE BUFFER IN A NEURAL NETWORKS ACCELERATOR FRAMEWORK [patent_app_type] => utility [patent_app_number] => 17/039653 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/039653
Reconfigurable hardware buffer in a neural networks accelerator framework Sep 29, 2020 Issued
Array ( [id] => 18564011 [patent_doc_number] => 11729272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Hart-enabled device with reduced communication lines and break extension protocol [patent_app_type] => utility [patent_app_number] => 17/032703 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7070 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17032703 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/032703
Hart-enabled device with reduced communication lines and break extension protocol Sep 24, 2020 Issued
Array ( [id] => 17223573 [patent_doc_number] => 11176074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Chip and interface conversion device [patent_app_type] => utility [patent_app_number] => 17/023397 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6868 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023397
Chip and interface conversion device Sep 16, 2020 Issued
Array ( [id] => 17715406 [patent_doc_number] => 11379397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Transmission device capable of control feedback and control feedback method [patent_app_type] => utility [patent_app_number] => 17/023233 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3127 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023233 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/023233
Transmission device capable of control feedback and control feedback method Sep 15, 2020 Issued
Array ( [id] => 16630466 [patent_doc_number] => 20210049119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => Memory Modules and Systems with Variable-Width Data Ranks and Configurable Data-Rank Timing [patent_app_type] => utility [patent_app_number] => 17/021024 [patent_app_country] => US [patent_app_date] => 2020-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17021024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/021024
Memory module and registered clock driver with configurable data-rank timing Sep 14, 2020 Issued
Array ( [id] => 18304283 [patent_doc_number] => 11626196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-04-11 [patent_title] => Card-type storage device with data uploading function and data uploading method applied thereto [patent_app_type] => utility [patent_app_number] => 17/010868 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010868 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/010868
Card-type storage device with data uploading function and data uploading method applied thereto Sep 2, 2020 Issued
Array ( [id] => 17430435 [patent_doc_number] => 20220058144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => INTERFACE FOR SEMICONDUCTOR DEVICE AND INTERFACING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/999055 [patent_app_country] => US [patent_app_date] => 2020-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999055 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999055
Interface for semiconductor device and interfacing method thereof Aug 19, 2020 Issued
Array ( [id] => 17955243 [patent_doc_number] => 11481350 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-25 [patent_title] => Network chip yield improvement architectures and techniques [patent_app_type] => utility [patent_app_number] => 16/940003 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 23702 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16940003 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/940003
Network chip yield improvement architectures and techniques Jul 26, 2020 Issued
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