Search

Aurangzeb Hassan

Examiner (ID: 18198, Phone: (571)272-8625 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2182, 2184
Total Applications
858
Issued Applications
624
Pending Applications
78
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17091624 [patent_doc_number] => 11119814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Dynamic assignment of interrupts based on input/output metrics [patent_app_type] => utility [patent_app_number] => 16/382182 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5481 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382182 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382182
Dynamic assignment of interrupts based on input/output metrics Apr 10, 2019 Issued
Array ( [id] => 17091624 [patent_doc_number] => 11119814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Dynamic assignment of interrupts based on input/output metrics [patent_app_type] => utility [patent_app_number] => 16/382182 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5481 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382182 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382182
Dynamic assignment of interrupts based on input/output metrics Apr 10, 2019 Issued
Array ( [id] => 17091624 [patent_doc_number] => 11119814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Dynamic assignment of interrupts based on input/output metrics [patent_app_type] => utility [patent_app_number] => 16/382182 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5481 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382182 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382182
Dynamic assignment of interrupts based on input/output metrics Apr 10, 2019 Issued
Array ( [id] => 17046857 [patent_doc_number] => 11100038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Method and apparatus for providing interface [patent_app_type] => utility [patent_app_number] => 16/381309 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 21260 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381309 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381309
Method and apparatus for providing interface Apr 10, 2019 Issued
Array ( [id] => 17091624 [patent_doc_number] => 11119814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Dynamic assignment of interrupts based on input/output metrics [patent_app_type] => utility [patent_app_number] => 16/382182 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5481 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382182 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382182
Dynamic assignment of interrupts based on input/output metrics Apr 10, 2019 Issued
Array ( [id] => 16895095 [patent_doc_number] => 11036649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Network interface card resource partitioning [patent_app_type] => utility [patent_app_number] => 16/374952 [patent_app_country] => US [patent_app_date] => 2019-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16374952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/374952
Network interface card resource partitioning Apr 3, 2019 Issued
Array ( [id] => 16362873 [patent_doc_number] => 20200319624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => SYSTEMS AND METHODS FOR POWER AND COOLING CONTROL OF EXPANSION CHASSIS USING HOST INTERFACE CARD SIDEBAND SIGNALS [patent_app_type] => utility [patent_app_number] => 16/373400 [patent_app_country] => US [patent_app_date] => 2019-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5001 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16373400 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/373400
Systems and methods for power and cooling control of expansion chassis using host interface card sideband signals Apr 1, 2019 Issued
Array ( [id] => 16346342 [patent_doc_number] => 20200310993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SHARED ACCELERATOR MEMORY SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 16/370587 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370587 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370587
Shared accelerator memory systems and methods Mar 28, 2019 Issued
Array ( [id] => 14902397 [patent_doc_number] => 20190294964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/357438 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357438 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/357438
Computing system for performing efficient machine learning processing Mar 18, 2019 Issued
Array ( [id] => 15047469 [patent_doc_number] => 20190334739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/277369 [patent_app_country] => US [patent_app_date] => 2019-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16277369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/277369
Communication system Feb 14, 2019 Issued
Array ( [id] => 16446961 [patent_doc_number] => 10838890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Acceleration resource processing method and apparatus, and network functions virtualization system [patent_app_type] => utility [patent_app_number] => 16/234607 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9998 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234607
Acceleration resource processing method and apparatus, and network functions virtualization system Dec 27, 2018 Issued
Array ( [id] => 14235411 [patent_doc_number] => 20190129878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => BUS ADDRESS ASSIGNMENT [patent_app_type] => utility [patent_app_number] => 16/234524 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234524
Bus address assignment Dec 26, 2018 Issued
Array ( [id] => 15412705 [patent_doc_number] => 20200026675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => Switching Method and Related Electronic System [patent_app_type] => utility [patent_app_number] => 16/198657 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16198657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/198657
Switching Method and Related Electronic System Nov 20, 2018 Abandoned
Array ( [id] => 14347607 [patent_doc_number] => 20190155776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => TRANSMISSION APPARATUS AND TRANSMISSION METHOD [patent_app_type] => utility [patent_app_number] => 16/193621 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16193621 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/193621
Transmission apparatus and transmission method Nov 15, 2018 Issued
Array ( [id] => 14629207 [patent_doc_number] => 20190227971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => ARCHITECTURE FOR CONSOLIDATING MULTIPLE SOURCES OF LOW-BANDWIDTH DATA OVER A SERIAL BUS [patent_app_type] => utility [patent_app_number] => 16/193731 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16193731 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/193731
ARCHITECTURE FOR CONSOLIDATING MULTIPLE SOURCES OF LOW-BANDWIDTH DATA OVER A SERIAL BUS Nov 15, 2018 Abandoned
Array ( [id] => 14347593 [patent_doc_number] => 20190155769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => SENSOR DATA PIPELINING [patent_app_type] => utility [patent_app_number] => 16/193501 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16193501 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/193501
Sensor data pipelining Nov 15, 2018 Issued
Array ( [id] => 15903203 [patent_doc_number] => 20200151121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => OUTPUT PROCESSOR FOR TRANSACTION PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/186744 [patent_app_country] => US [patent_app_date] => 2018-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186744 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186744
Output processor for transaction processing system Nov 11, 2018 Issued
Array ( [id] => 14411503 [patent_doc_number] => 20190171595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => BIT-INTERLEAVED BI-DIRECTIONAL TRANSMISSIONS ON A MULTI-DROP BUS FOR TIME-CRITICAL DATA EXCHANGE [patent_app_type] => utility [patent_app_number] => 16/184284 [patent_app_country] => US [patent_app_date] => 2018-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16184284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/184284
Bit-interleaved bi-directional transmissions on a multi-drop bus for time-critical data exchange Nov 7, 2018 Issued
Array ( [id] => 14282413 [patent_doc_number] => 20190138491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => DATA COMMUNICATION APPARATUS [patent_app_type] => utility [patent_app_number] => 16/180567 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16180567 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/180567
Data communication apparatus Nov 4, 2018 Issued
Array ( [id] => 13992545 [patent_doc_number] => 20190065430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => SYSTEM ON CHIP FOR PACKETIZING MULTIPLE BYTES AND DATA PROCESSING SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/173040 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173040 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/173040
System on chip for packetizing multiple bytes and data processing system including the same Oct 28, 2018 Issued
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