Search

Aurangzeb Hassan

Examiner (ID: 18198, Phone: (571)272-8625 , Office: P/2184 )

Most Active Art Unit
2184
Art Unit(s)
2182, 2184
Total Applications
858
Issued Applications
624
Pending Applications
78
Abandoned Applications
179

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6999464 [patent_doc_number] => 20050138233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Direct memory access control' [patent_app_type] => utility [patent_app_number] => 10/742938 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4182 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138233.pdf [firstpage_image] =>[orig_patent_app_number] => 10742938 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742938
Direct memory access control Dec 22, 2003 Abandoned
Array ( [id] => 6999488 [patent_doc_number] => 20050138244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Lower bound algorithm for operation scheduling' [patent_app_type] => utility [patent_app_number] => 10/745259 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3158 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138244.pdf [firstpage_image] =>[orig_patent_app_number] => 10745259 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/745259
Lower bound algorithm for operation scheduling Dec 22, 2003 Abandoned
Array ( [id] => 6999610 [patent_doc_number] => 20050138302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Method and apparatus for logic analyzer observability of buffered memory module links' [patent_app_type] => utility [patent_app_number] => 10/746532 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4451 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138302.pdf [firstpage_image] =>[orig_patent_app_number] => 10746532 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746532
Method and apparatus for logic analyzer observability of buffered memory module links Dec 22, 2003 Abandoned
Array ( [id] => 6997214 [patent_doc_number] => 20050136992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Providing access to auxiliary hardware in multiprocessor devices' [patent_app_type] => utility [patent_app_number] => 10/744623 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1648 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20050136992.pdf [firstpage_image] =>[orig_patent_app_number] => 10744623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/744623
Providing access to auxiliary hardware in multiprocessor devices Dec 22, 2003 Abandoned
Array ( [id] => 6999449 [patent_doc_number] => 20050138221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Handling redundant paths among devices' [patent_app_type] => utility [patent_app_number] => 10/746657 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5448 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138221.pdf [firstpage_image] =>[orig_patent_app_number] => 10746657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746657
Handling redundant paths among devices Dec 22, 2003 Abandoned
Array ( [id] => 6999471 [patent_doc_number] => 20050138238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Flow control interface' [patent_app_type] => utility [patent_app_number] => 10/745270 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5527 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138238.pdf [firstpage_image] =>[orig_patent_app_number] => 10745270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/745270
Flow control interface Dec 21, 2003 Abandoned
Array ( [id] => 7174077 [patent_doc_number] => 20050123139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'METHOD FOR MANAGING A BUFFER MEMORY IN A CRYPTO ENGINE' [patent_app_type] => utility [patent_app_number] => 10/707381 [patent_app_country] => US [patent_app_date] => 2003-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2371 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20050123139.pdf [firstpage_image] =>[orig_patent_app_number] => 10707381 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707381
METHOD FOR MANAGING A BUFFER MEMORY IN A CRYPTO ENGINE Dec 8, 2003 Abandoned
Array ( [id] => 465720 [patent_doc_number] => 07243170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-10 [patent_title] => 'Method and circuit for reading and writing an instruction buffer' [patent_app_type] => utility [patent_app_number] => 10/707149 [patent_app_country] => US [patent_app_date] => 2003-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6750 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243170.pdf [firstpage_image] =>[orig_patent_app_number] => 10707149 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707149
Method and circuit for reading and writing an instruction buffer Nov 23, 2003 Issued
Array ( [id] => 7676245 [patent_doc_number] => 20040153582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Data processor and memory card' [patent_app_type] => new [patent_app_number] => 10/714936 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6511 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20040153582.pdf [firstpage_image] =>[orig_patent_app_number] => 10714936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714936
Data processor and memory card Nov 17, 2003 Abandoned
Array ( [id] => 457819 [patent_doc_number] => 07249203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-24 [patent_title] => 'Programmatic time-gap defect detection apparatus and method' [patent_app_type] => utility [patent_app_number] => 10/715340 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6923 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/249/07249203.pdf [firstpage_image] =>[orig_patent_app_number] => 10715340 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/715340
Programmatic time-gap defect detection apparatus and method Nov 16, 2003 Issued
Array ( [id] => 116342 [patent_doc_number] => 07721024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-18 [patent_title] => 'System and method for exiting from an interrupt mode in a multiple processor system' [patent_app_type] => utility [patent_app_number] => 10/706657 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3063 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/721/07721024.pdf [firstpage_image] =>[orig_patent_app_number] => 10706657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706657
System and method for exiting from an interrupt mode in a multiple processor system Nov 11, 2003 Issued
Array ( [id] => 7107148 [patent_doc_number] => 20050108445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Systems and methods for implementing device regionalization' [patent_app_type] => utility [patent_app_number] => 10/700126 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4500 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108445.pdf [firstpage_image] =>[orig_patent_app_number] => 10700126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/700126
Systems and methods for implementing device regionalization Nov 2, 2003 Abandoned
10/698525 Flexible channel bonding Nov 2, 2003 Abandoned
Array ( [id] => 6919824 [patent_doc_number] => 20050097291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Multiple data rate bus using return clock' [patent_app_type] => utility [patent_app_number] => 10/699473 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6595 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097291.pdf [firstpage_image] =>[orig_patent_app_number] => 10699473 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/699473
Multiple data rate bus using return clock Oct 30, 2003 Abandoned
Array ( [id] => 623157 [patent_doc_number] => 07143199 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Framing and word alignment for partially reconfigurable programmable circuits' [patent_app_type] => utility [patent_app_number] => 10/699012 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4419 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143199.pdf [firstpage_image] =>[orig_patent_app_number] => 10699012 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/699012
Framing and word alignment for partially reconfigurable programmable circuits Oct 30, 2003 Issued
Array ( [id] => 58405 [patent_doc_number] => 07769922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Processing system streaming data handling system and stream register' [patent_app_type] => utility [patent_app_number] => 10/697996 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3873 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/769/07769922.pdf [firstpage_image] =>[orig_patent_app_number] => 10697996 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697996
Processing system streaming data handling system and stream register Oct 29, 2003 Issued
Array ( [id] => 7746144 [patent_doc_number] => 08108564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'System and method for a configurable interface controller' [patent_app_type] => utility [patent_app_number] => 10/697903 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 59 [patent_no_of_words] => 17743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108564.pdf [firstpage_image] =>[orig_patent_app_number] => 10697903 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697903
System and method for a configurable interface controller Oct 29, 2003 Issued
Array ( [id] => 7421265 [patent_doc_number] => 20040160845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Method and apparatus to reduce access time in synchronous FIFOS with zero latency overhead' [patent_app_type] => new [patent_app_number] => 10/697958 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20040160845.pdf [firstpage_image] =>[orig_patent_app_number] => 10697958 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697958
Method and apparatus to reduce access time in synchronous FIFOS with zero latency overhead Oct 29, 2003 Abandoned
Array ( [id] => 6919758 [patent_doc_number] => 20050097248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'System and method for establishing a communication between a peripheral device and a wireless device' [patent_app_type] => utility [patent_app_number] => 10/697593 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6703 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097248.pdf [firstpage_image] =>[orig_patent_app_number] => 10697593 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697593
System and method for establishing a communication between a peripheral device and a wireless device Oct 28, 2003 Abandoned
Array ( [id] => 7602001 [patent_doc_number] => 07237042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Mechanism for generating a virtual identifier' [patent_app_type] => utility [patent_app_number] => 10/697540 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4392 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237042.pdf [firstpage_image] =>[orig_patent_app_number] => 10697540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697540
Mechanism for generating a virtual identifier Oct 28, 2003 Issued
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