Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19688992 [patent_doc_number] => 20250007537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/887114 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887114 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887114
EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES Sep 16, 2024 Pending
Array ( [id] => 19820737 [patent_doc_number] => 20250078944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => IMAGE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/815077 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815077
IMAGE DISPLAY DEVICE Aug 25, 2024 Pending
Array ( [id] => 19633490 [patent_doc_number] => 20240411939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => RECOVERING DATA FROM DE-SEQUENCED ENCODED DATA SLICES [patent_app_type] => utility [patent_app_number] => 18/808433 [patent_app_country] => US [patent_app_date] => 2024-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18808433 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/808433
RECOVERING DATA FROM DE-SEQUENCED ENCODED DATA SLICES Aug 18, 2024 Pending
Array ( [id] => 20461966 [patent_doc_number] => 20260011395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => TESTING METHOD AND TESTING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/791443 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791443
TESTING METHOD AND TESTING SYSTEM Jul 31, 2024 Pending
Array ( [id] => 19590754 [patent_doc_number] => 20240388311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => TWO-LEVEL ERROR CORRECTING CODE WITH SHARING OF CHECK-BITS [patent_app_type] => utility [patent_app_number] => 18/789063 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789063 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789063
TWO-LEVEL ERROR CORRECTING CODE WITH SHARING OF CHECK-BITS Jul 29, 2024 Pending
Array ( [id] => 20124289 [patent_doc_number] => 20250239320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => ERROR CORRECTION DISABLEMENT BY A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/776867 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776867
ERROR CORRECTION DISABLEMENT BY A MEMORY SYSTEM Jul 17, 2024 Pending
Array ( [id] => 19747138 [patent_doc_number] => 20250035703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION [patent_app_type] => utility [patent_app_number] => 18/770967 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6195 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770967
SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION Jul 11, 2024 Pending
Array ( [id] => 19697422 [patent_doc_number] => 20250015967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => CONFIGURATION SCHEME FOR LINK ESTABLISHMENT [patent_app_type] => utility [patent_app_number] => 18/768851 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768851 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768851
CONFIGURATION SCHEME FOR LINK ESTABLISHMENT Jul 9, 2024 Pending
Array ( [id] => 20063107 [patent_doc_number] => 20250201329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => DETECTING ERRORS WITHIN DATA PATH CIRCUITRY OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/766219 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766219
DETECTING ERRORS WITHIN DATA PATH CIRCUITRY OF A MEMORY DEVICE Jul 7, 2024 Pending
Array ( [id] => 20455787 [patent_doc_number] => 12518847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Centralized error correction circuit [patent_app_type] => utility [patent_app_number] => 18/647867 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14576 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647867
Centralized error correction circuit Jun 6, 2024 Issued
Array ( [id] => 19696119 [patent_doc_number] => 20250014664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => STORAGE DEVICE DETERMINING DETERIORATION WORDLINE, AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/677544 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14469 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677544 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677544
STORAGE DEVICE DETERMINING DETERIORATION WORDLINE, AND METHOD OF OPERATING THE SAME May 28, 2024 Pending
Array ( [id] => 19605691 [patent_doc_number] => 20240396571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => ERROR PROTECTION FOR MANAGED MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/672533 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672533 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672533
ERROR PROTECTION FOR MANAGED MEMORY DEVICES May 22, 2024 Pending
Array ( [id] => 19893848 [patent_doc_number] => 20250119160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => LDPC DECODER AND MINIMUM VALUE SEARCHING METHOD [patent_app_type] => utility [patent_app_number] => 18/664686 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664686
LDPC DECODER AND MINIMUM VALUE SEARCHING METHOD May 14, 2024 Pending
Array ( [id] => 20360647 [patent_doc_number] => 12476655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Low-density parity check decoder [patent_app_type] => utility [patent_app_number] => 18/664711 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3780 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664711
Low-density parity check decoder May 14, 2024 Issued
Array ( [id] => 20368138 [patent_doc_number] => 20250357950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-20 [patent_title] => DECODING A SIGNAL BASED ON SOFT SYNDROME DECODING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/663882 [patent_app_country] => US [patent_app_date] => 2024-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18663882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/663882
DECODING A SIGNAL BASED ON SOFT SYNDROME DECODING TECHNIQUES May 13, 2024 Pending
Array ( [id] => 20339439 [patent_doc_number] => 20250343559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-06 [patent_title] => SINGLE-INDEX PARITY CHECK FOR POLAR ENCODING [patent_app_type] => utility [patent_app_number] => 18/653759 [patent_app_country] => US [patent_app_date] => 2024-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18653759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/653759
SINGLE-INDEX PARITY CHECK FOR POLAR ENCODING May 1, 2024 Pending
Array ( [id] => 20010883 [patent_doc_number] => 20250149105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MEMORY DEVICE FOR SUPPORTING TRIPLE ADJACENT ERROR DETECTION, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/648882 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648882 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648882
MEMORY DEVICE FOR SUPPORTING TRIPLE ADJACENT ERROR DETECTION, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF Apr 28, 2024 Pending
Array ( [id] => 20064284 [patent_doc_number] => 20250202506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 2/3 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647812 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647812 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647812
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 2/3 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 20064283 [patent_doc_number] => 20250202505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 3/4 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647792 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647792 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647792
SYSTEMS AND METHODS FOR BLOCK-KRONECKER BASED LOW DENSITY PARITY CHECK (LDPC) CODE WITH 3/4 CODE RATE Apr 25, 2024 Pending
Array ( [id] => 19758740 [patent_doc_number] => 20250047305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SYSTEM AND METHOD FOR LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE [patent_app_type] => utility [patent_app_number] => 18/647699 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15452 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647699 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647699
SYSTEM AND METHOD FOR LOW DENSITY PARITY CHECK (LDPC) CODE WITH 5/6 CODE RATE Apr 25, 2024 Pending
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