
Austin Murata
Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )
| Most Active Art Unit | 1712 |
| Art Unit(s) | 1712, 1792 |
| Total Applications | 853 |
| Issued Applications | 467 |
| Pending Applications | 93 |
| Abandoned Applications | 315 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18494595
[patent_doc_number] => 11700020
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Fault tolerant quantum error correction with linear codes
[patent_app_type] => utility
[patent_app_number] => 16/663018
[patent_app_country] => US
[patent_app_date] => 2019-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 40
[patent_no_of_words] => 34764
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16663018
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/663018 | Fault tolerant quantum error correction with linear codes | Oct 23, 2019 | Issued |
Array
(
[id] => 15505253
[patent_doc_number] => 20200052815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-13
[patent_title] => TRANSMITTING/RECEIVING SYSTEM AND BROADCAST SIGNAL PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/659472
[patent_app_country] => US
[patent_app_date] => 2019-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 45163
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659472
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/659472 | TRANSMITTING/RECEIVING SYSTEM AND BROADCAST SIGNAL PROCESSING METHOD | Oct 20, 2019 | Abandoned |
Array
(
[id] => 17390264
[patent_doc_number] => 20220038116
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-03
[patent_title] => OFFSET VALUE DETERMINATION IN A CHECK NODE PROCESSING UNIT FOR MESSAGE-PASSING DECODING OF NON-BINARY CODES
[patent_app_type] => utility
[patent_app_number] => 17/276255
[patent_app_country] => US
[patent_app_date] => 2019-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9919
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17276255
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/276255 | Offset value determination in a check node processing unit for message-passing decoding of non-binary codes | Oct 6, 2019 | Issued |
Array
(
[id] => 16333189
[patent_doc_number] => 20200304155
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => ERROR CORRECTION DECODER AND MEMORY SYSTEM HAVING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/590222
[patent_app_country] => US
[patent_app_date] => 2019-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18341
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16590222
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/590222 | Error correction decoder and memory system having the same | Sep 30, 2019 | Issued |
Array
(
[id] => 17528631
[patent_doc_number] => 11301319
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-12
[patent_title] => Memory device and memory system having multiple error correction functions, and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 16/575615
[patent_app_country] => US
[patent_app_date] => 2019-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8973
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575615
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/575615 | Memory device and memory system having multiple error correction functions, and operating method thereof | Sep 18, 2019 | Issued |
Array
(
[id] => 17091648
[patent_doc_number] => 11119838
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-14
[patent_title] => Techniques for handling errors in persistent memory
[patent_app_type] => utility
[patent_app_number] => 16/572382
[patent_app_country] => US
[patent_app_date] => 2019-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 13435
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572382
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/572382 | Techniques for handling errors in persistent memory | Sep 15, 2019 | Issued |
Array
(
[id] => 16674722
[patent_doc_number] => 20210063486
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => Failure Prediction System and Method
[patent_app_type] => utility
[patent_app_number] => 16/553248
[patent_app_country] => US
[patent_app_date] => 2019-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5838
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553248
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/553248 | Failure prediction system and method | Aug 27, 2019 | Issued |
Array
(
[id] => 15971043
[patent_doc_number] => 20200169273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-28
[patent_title] => APPARATUS AND METHOD FOR ESTIMATING BURST ERROR
[patent_app_type] => utility
[patent_app_number] => 16/553445
[patent_app_country] => US
[patent_app_date] => 2019-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3894
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553445
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/553445 | APPARATUS AND METHOD FOR ESTIMATING BURST ERROR | Aug 27, 2019 | Abandoned |
Array
(
[id] => 15094257
[patent_doc_number] => 20190341940
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-07
[patent_title] => BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
[patent_app_type] => utility
[patent_app_number] => 16/516514
[patent_app_country] => US
[patent_app_date] => 2019-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5828
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16516514
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/516514 | Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 64-symbol mapping, and bit interleaving method using same | Jul 18, 2019 | Issued |
Array
(
[id] => 15094255
[patent_doc_number] => 20190341939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-07
[patent_title] => BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 2/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME
[patent_app_type] => utility
[patent_app_number] => 16/512679
[patent_app_country] => US
[patent_app_date] => 2019-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5733
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512679
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/512679 | Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 64-symbol mapping, and bit interleaving method using same | Jul 15, 2019 | Issued |
Array
(
[id] => 17001322
[patent_doc_number] => 11080132
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-03
[patent_title] => Generating error checking data for error detection during modification of data in a memory sub-system
[patent_app_type] => utility
[patent_app_number] => 16/510559
[patent_app_country] => US
[patent_app_date] => 2019-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 12213
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510559
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/510559 | Generating error checking data for error detection during modification of data in a memory sub-system | Jul 11, 2019 | Issued |
Array
(
[id] => 17239379
[patent_doc_number] => 11183267
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-23
[patent_title] => Recovery management of retired super management units
[patent_app_type] => utility
[patent_app_number] => 16/510778
[patent_app_country] => US
[patent_app_date] => 2019-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8225
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510778
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/510778 | Recovery management of retired super management units | Jul 11, 2019 | Issued |
Array
(
[id] => 17422971
[patent_doc_number] => 11256425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-22
[patent_title] => Flash memory controller, flash memory module and associated electronic device
[patent_app_type] => utility
[patent_app_number] => 16/505701
[patent_app_country] => US
[patent_app_date] => 2019-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11568
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16505701
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/505701 | Flash memory controller, flash memory module and associated electronic device | Jul 7, 2019 | Issued |
Array
(
[id] => 15047297
[patent_doc_number] => 20190334653
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-31
[patent_title] => TRANSMITTER AND SHORTENING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/504103
[patent_app_country] => US
[patent_app_date] => 2019-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29092
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 382
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16504103
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/504103 | Transmitter and shortening method thereof | Jul 4, 2019 | Issued |
Array
(
[id] => 17942404
[patent_doc_number] => 11476870
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-18
[patent_title] => Variable node processing methods and devices for message-passing decoding of non-binary codes
[patent_app_type] => utility
[patent_app_number] => 17/257191
[patent_app_country] => US
[patent_app_date] => 2019-07-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 14869
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17257191
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/257191 | Variable node processing methods and devices for message-passing decoding of non-binary codes | Jul 3, 2019 | Issued |
Array
(
[id] => 16910401
[patent_doc_number] => 11042441
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-22
[patent_title] => Stripe mapping in memory
[patent_app_type] => utility
[patent_app_number] => 16/458578
[patent_app_country] => US
[patent_app_date] => 2019-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6417
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16458578
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/458578 | Stripe mapping in memory | Jun 30, 2019 | Issued |
Array
(
[id] => 16543393
[patent_doc_number] => 20200409808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => Systems And Methods For Evaluating Integrity Of Adjacent Sub Blocks Of Data Storage Apparatuses
[patent_app_type] => utility
[patent_app_number] => 16/457166
[patent_app_country] => US
[patent_app_date] => 2019-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10865
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16457166
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/457166 | Systems and methods for evaluating integrity of adjacent sub blocks of data storage apparatuses | Jun 27, 2019 | Issued |
Array
(
[id] => 16667169
[patent_doc_number] => 10936415
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-02
[patent_title] => Error correction scheme in flash memory
[patent_app_type] => utility
[patent_app_number] => 16/455857
[patent_app_country] => US
[patent_app_date] => 2019-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8305
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455857
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/455857 | Error correction scheme in flash memory | Jun 27, 2019 | Issued |
Array
(
[id] => 17108083
[patent_doc_number] => 11128314
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-21
[patent_title] => Error characteristic estimation for NAND flash
[patent_app_type] => utility
[patent_app_number] => 16/450724
[patent_app_country] => US
[patent_app_date] => 2019-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7713
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450724
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/450724 | Error characteristic estimation for NAND flash | Jun 23, 2019 | Issued |
Array
(
[id] => 14813803
[patent_doc_number] => 20190273511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-05
[patent_title] => GENERATION OF SPATIALLY-COUPLED QUASI-CYCLIC LDPC CODES
[patent_app_type] => utility
[patent_app_number] => 16/417812
[patent_app_country] => US
[patent_app_date] => 2019-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10593
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16417812
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/417812 | GENERATION OF SPATIALLY-COUPLED QUASI-CYCLIC LDPC CODES | May 20, 2019 | Abandoned |