Search

Austin Murata

Examiner (ID: 3702, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1792, 1712
Total Applications
876
Issued Applications
483
Pending Applications
87
Abandoned Applications
318

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17810971 [patent_doc_number] => 20220262806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) MEMORY CELL AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/177164 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17177164 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/177164
Silicon-oxide-nitride-oxide-silicon (SONOS) memory cell and forming method thereof Feb 15, 2021 Issued
Array ( [id] => 20375340 [patent_doc_number] => 12482784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Method for controlling boat/strip type solder ball placement system [patent_app_type] => utility [patent_app_number] => 17/905274 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17905274 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/905274
Method for controlling boat/strip type solder ball placement system Feb 15, 2021 Issued
Array ( [id] => 16873612 [patent_doc_number] => 20210167079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => METHODS OF FORMING A STAIRCASE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/173405 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173405 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173405
Methods of forming a staircase structure Feb 10, 2021 Issued
Array ( [id] => 17803258 [patent_doc_number] => 11417570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 17/172325 [patent_app_country] => US [patent_app_date] => 2021-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 10203 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17172325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/172325
Wafer processing method Feb 9, 2021 Issued
Array ( [id] => 17683391 [patent_doc_number] => 11367656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 17/168333 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4417 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168333 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168333
Wafer processing method Feb 4, 2021 Issued
Array ( [id] => 17115658 [patent_doc_number] => 20210296255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => MEMORY DEVICE AND METHOD OF MANUFACTURING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/163759 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17163759 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/163759
Memory device and method of manufacturing memory device Jan 31, 2021 Issued
Array ( [id] => 17716801 [patent_doc_number] => 11380802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 17/160435 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 112 [patent_no_of_words] => 52875 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160435 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160435
Method for manufacturing semiconductor device Jan 27, 2021 Issued
Array ( [id] => 17025382 [patent_doc_number] => 20210249254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS [patent_app_type] => utility [patent_app_number] => 17/157704 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157704
OXIDE-NITRIDE-OXIDE STACK HAVING MULTIPLE OXYNITRIDE LAYERS Jan 24, 2021 Abandoned
Array ( [id] => 17908591 [patent_doc_number] => 11462452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Chip package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/156626 [patent_app_country] => US [patent_app_date] => 2021-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3717 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156626
Chip package structure and manufacturing method thereof Jan 23, 2021 Issued
Array ( [id] => 18032232 [patent_doc_number] => 11515432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Cool electron erasing in thin-film storage transistors [patent_app_type] => utility [patent_app_number] => 17/155673 [patent_app_country] => US [patent_app_date] => 2021-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 5122 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17155673 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/155673
Cool electron erasing in thin-film storage transistors Jan 21, 2021 Issued
Array ( [id] => 16920496 [patent_doc_number] => 20210193588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => INTEGRATED SHIELD PACKAGE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/140614 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140614
Integrated shield package and method Jan 3, 2021 Issued
Array ( [id] => 17645253 [patent_doc_number] => 20220172992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => SEMICONDUCTOR DIE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/137298 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137298 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137298
Semiconductor die and manufacturing method of semiconductor device Dec 28, 2020 Issued
Array ( [id] => 18500581 [patent_doc_number] => 20230223376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => IC CHIP MOUNTING DEVICE AND IC CHIP MOUNTING METHOD [patent_app_type] => utility [patent_app_number] => 17/783819 [patent_app_country] => US [patent_app_date] => 2020-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17783819 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/783819
IC CHIP MOUNTING DEVICE AND IC CHIP MOUNTING METHOD Dec 24, 2020 Pending
Array ( [id] => 18874873 [patent_doc_number] => 11862696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/120951 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 5569 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 368 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120951 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120951
Semiconductor storage device Dec 13, 2020 Issued
Array ( [id] => 17551671 [patent_doc_number] => 20220123013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/116638 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116638
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION THEREOF Dec 8, 2020 Abandoned
Array ( [id] => 16904796 [patent_doc_number] => 20210183712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SUBSTRATE TREATMENT METHOD AND SUBSTRATE TREATMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 17/114717 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114717
Substrate treatment method and substrate treatment system Dec 7, 2020 Issued
Array ( [id] => 17745704 [patent_doc_number] => 11393786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Method for manufacturing electronic chips [patent_app_type] => utility [patent_app_number] => 17/111198 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 6954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111198
Method for manufacturing electronic chips Dec 2, 2020 Issued
Array ( [id] => 17745703 [patent_doc_number] => 11393785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Method for manufacturing electronic chips [patent_app_type] => utility [patent_app_number] => 17/110063 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 7531 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17110063 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/110063
Method for manufacturing electronic chips Dec 1, 2020 Issued
Array ( [id] => 19138005 [patent_doc_number] => 11972980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Singulation systems and related methods [patent_app_type] => utility [patent_app_number] => 17/104302 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4461 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104302 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104302
Singulation systems and related methods Nov 24, 2020 Issued
Array ( [id] => 17630844 [patent_doc_number] => 20220165859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => INTEGRATED CHIP WITH A GATE STRUCTURE OVER A RECESS [patent_app_type] => utility [patent_app_number] => 16/953921 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953921
Integrated chip with a gate structure over a recess Nov 19, 2020 Issued
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