Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17417879 [patent_doc_number] => 20220052784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => DATA PROCESSING IN CHANNEL DECODING [patent_app_type] => utility [patent_app_number] => 17/420039 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17420039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/420039
DATA PROCESSING IN CHANNEL DECODING Jan 13, 2019 Abandoned
Array ( [id] => 14218611 [patent_doc_number] => 20190121690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => POOL-LEVEL SOLID STATE DRIVE ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 16/230888 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16230888 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/230888
Pool-level solid state drive error correction Dec 20, 2018 Issued
Array ( [id] => 14935205 [patent_doc_number] => 20190303240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => CONTROLLER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/221896 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221896 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221896
Controller and operating method thereof Dec 16, 2018 Issued
Array ( [id] => 16080211 [patent_doc_number] => 20200194092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => MULTI-DIMENSIONAL USAGE SPACE TESTING OF MEMORY COMPONENTS [patent_app_type] => utility [patent_app_number] => 16/222295 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222295 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222295
Multi-dimensional usage space testing of memory components Dec 16, 2018 Issued
Array ( [id] => 14472869 [patent_doc_number] => 20190188079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => DURABLE BLOCK STORAGE IN DATA CENTER ACCESS NODES WITH INLINE ERASURE CODING [patent_app_type] => utility [patent_app_number] => 16/215178 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215178
Durable block storage in data center access nodes with inline erasure coding Dec 9, 2018 Issued
Array ( [id] => 16017501 [patent_doc_number] => 20200183594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => AGE-BASED REFRESH OF FIRMWARE [patent_app_type] => utility [patent_app_number] => 16/215327 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215327
Age-based refresh of firmware Dec 9, 2018 Issued
Array ( [id] => 16433600 [patent_doc_number] => 10833703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => DMA transfer apparatus, method of controlling the same, communication apparatus, method of controlling the same, and non-transitory computer-readable storage medium [patent_app_type] => utility [patent_app_number] => 16/213024 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17220 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213024
DMA transfer apparatus, method of controlling the same, communication apparatus, method of controlling the same, and non-transitory computer-readable storage medium Dec 6, 2018 Issued
Array ( [id] => 16291380 [patent_doc_number] => 10768223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Semiconductor device and memory module including the semiconductor device [patent_app_type] => utility [patent_app_number] => 16/213771 [patent_app_country] => US [patent_app_date] => 2018-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7816 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16213771 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/213771
Semiconductor device and memory module including the semiconductor device Dec 6, 2018 Issued
Array ( [id] => 15042935 [patent_doc_number] => 20190332472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => MEMORY DEVICE, A MEMORY SYSTEM AND AN OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/196471 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16196471 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/196471
Memory device, a memory system and an operating method thereof Nov 19, 2018 Issued
Array ( [id] => 18372385 [patent_doc_number] => 11652571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-16 [patent_title] => Incremental cyclic redundancy (CRC) process [patent_app_type] => utility [patent_app_number] => 16/197124 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3162 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197124
Incremental cyclic redundancy (CRC) process Nov 19, 2018 Issued
Array ( [id] => 14999679 [patent_doc_number] => 20190318797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => MEMORY DEVICE INCLUDING LOAD GENERATOR AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/192989 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192989 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192989
Memory device including load generator and method of operating the same Nov 15, 2018 Issued
Array ( [id] => 14349871 [patent_doc_number] => 20190156908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => ENABLING HIGH AT-SPEED TEST COVERAGE OF FUNCTIONAL MEMORY INTERFACE LOGIC BY SELECTIVE USAGE OF TEST PATHS [patent_app_type] => utility [patent_app_number] => 16/192796 [patent_app_country] => US [patent_app_date] => 2018-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16192796 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/192796
Enabling high at-speed test coverage of functional memory interface logic by selective usage of test paths Nov 14, 2018 Issued
Array ( [id] => 13992159 [patent_doc_number] => 20190065237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => TRANSACTION IDENTIFICATION SYNCHRONIZATION [patent_app_type] => utility [patent_app_number] => 16/174686 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174686
TRANSACTION IDENTIFICATION SYNCHRONIZATION Oct 29, 2018 Abandoned
Array ( [id] => 13991925 [patent_doc_number] => 20190065120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => PROXYING READ REQUESTS WHEN PERFORMANCE OR AVAILABILITY FAILURE IS ANTICIPATED [patent_app_type] => utility [patent_app_number] => 16/175643 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175643
Proxying read requests when performance or availability failure is anticipated Oct 29, 2018 Issued
Array ( [id] => 15772707 [patent_doc_number] => 20200117371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => DETERMINING A READ APPARENT VOLTAGE INFECTOR PAGE AND INFECTED PAGE [patent_app_type] => utility [patent_app_number] => 16/157597 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7321 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157597
Determining a read apparent voltage infector page and infected page Oct 10, 2018 Issued
Array ( [id] => 15120791 [patent_doc_number] => 20190347028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => METHOD FOR PERFORMING PAGE AVAILABILITY MANAGEMENT OF MEMORY DEVICE, ASSOCIATED MEMORY DEVICE AND ELECTRONIC DEVICE, AND PAGE AVAILABILITY MANAGEMENT SYSTEM [patent_app_type] => utility [patent_app_number] => 16/141983 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141983 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141983
Method for performing page availability management of memory device, associated memory device and electronic device, and page availability management system Sep 25, 2018 Issued
Array ( [id] => 14506179 [patent_doc_number] => 20190196744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => NONVOLATILE MEMORY DEVICE, METHOD OF OPERATING NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/111813 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/111813
Nonvolatile memory device, method of operating nonvolatile memory device and storage device including the same Aug 23, 2018 Issued
Array ( [id] => 15609949 [patent_doc_number] => 10586039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Information processing apparatus [patent_app_type] => utility [patent_app_number] => 16/111694 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16111694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/111694
Information processing apparatus Aug 23, 2018 Issued
Array ( [id] => 16263293 [patent_doc_number] => 10754726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Tracking error-correction parity calculations [patent_app_type] => utility [patent_app_number] => 16/107187 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107187
Tracking error-correction parity calculations Aug 20, 2018 Issued
Array ( [id] => 16416611 [patent_doc_number] => 10824505 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-03 [patent_title] => ECC proxy extension and byte organization for multi-master systems [patent_app_type] => utility [patent_app_number] => 16/106691 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4848 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106691 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106691
ECC proxy extension and byte organization for multi-master systems Aug 20, 2018 Issued
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