Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16594572 [patent_doc_number] => 10903854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Replacing a subset of digits in a sequence [patent_app_type] => utility [patent_app_number] => 16/092926 [patent_app_country] => US [patent_app_date] => 2016-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16092926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/092926
Replacing a subset of digits in a sequence Apr 19, 2016 Issued
Array ( [id] => 12515628 [patent_doc_number] => 10002677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Test mode control circuit [patent_app_type] => utility [patent_app_number] => 15/133013 [patent_app_country] => US [patent_app_date] => 2016-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7696 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15133013 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/133013
Test mode control circuit Apr 18, 2016 Issued
Array ( [id] => 14153101 [patent_doc_number] => 10256944 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-09 [patent_title] => Controlling false packet acceptance [patent_app_type] => utility [patent_app_number] => 15/132900 [patent_app_country] => US [patent_app_date] => 2016-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 15951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132900 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132900
Controlling false packet acceptance Apr 18, 2016 Issued
Array ( [id] => 14427841 [patent_doc_number] => 10318726 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Systems and methods to provide security to one time program data [patent_app_type] => utility [patent_app_number] => 15/132026 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5405 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132026 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132026
Systems and methods to provide security to one time program data Apr 17, 2016 Issued
Array ( [id] => 11274417 [patent_doc_number] => 20160336965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'ERROR CORRECTION METHOD, SEMICONDUCTOR DEVICE, TRANSMISSION AND RECEPTION MODULE, AND TRANSMITTING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/092192 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6606 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092192 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092192
ERROR CORRECTION METHOD, SEMICONDUCTOR DEVICE, TRANSMISSION AND RECEPTION MODULE, AND TRANSMITTING APPARATUS Apr 5, 2016 Abandoned
Array ( [id] => 11984550 [patent_doc_number] => 20170288705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'SHARED MEMORY WITH ENHANCED ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 15/091195 [patent_app_country] => US [patent_app_date] => 2016-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15091195 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/091195
SHARED MEMORY WITH ENHANCED ERROR CORRECTION Apr 4, 2016 Abandoned
Array ( [id] => 11097542 [patent_doc_number] => 20160294512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'METHOD AND APPARATUS FOR ENCODING OR DECODING CHANNEL CODE IN A WIRELESS COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/091507 [patent_app_country] => US [patent_app_date] => 2016-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6356 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15091507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/091507
Method and apparatus for encoding or decoding channel code in a wireless communication system Apr 4, 2016 Issued
Array ( [id] => 11097540 [patent_doc_number] => 20160294509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'APPARATUS AND METHOD FOR SENDING AND RECEIVING BROADCAST SIGNALS' [patent_app_type] => utility [patent_app_number] => 15/091404 [patent_app_country] => US [patent_app_date] => 2016-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 27221 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15091404 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/091404
Apparatus and method for sending and receiving broadcast signals Apr 4, 2016 Issued
Array ( [id] => 11951073 [patent_doc_number] => 20170255223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'Ultra-Fast Autonomous Clock Monitoring Circuit for Safe and Secure Automotive Applications' [patent_app_type] => utility [patent_app_number] => 15/059341 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8557 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059341 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059341
Ultra-fast autonomous clock monitoring circuit for safe and secure automotive applications Mar 2, 2016 Issued
Array ( [id] => 14152897 [patent_doc_number] => 10256842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Technologies for correcting flipped bits for an error correction decode process [patent_app_type] => utility [patent_app_number] => 15/059642 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9730 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059642 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059642
Technologies for correcting flipped bits for an error correction decode process Mar 2, 2016 Issued
Array ( [id] => 12357120 [patent_doc_number] => 09954558 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-24 [patent_title] => Fast decoding of data stored in a flash memory [patent_app_type] => utility [patent_app_number] => 15/059397 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059397 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059397
Fast decoding of data stored in a flash memory Mar 2, 2016 Issued
Array ( [id] => 11070000 [patent_doc_number] => 20160266964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'PROGRAMMABLE LOGIC CIRCUIT DEVICE AND ERROR DETECTION METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/059355 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7819 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059355 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059355
PROGRAMMABLE LOGIC CIRCUIT DEVICE AND ERROR DETECTION METHOD THEREFOR Mar 2, 2016 Abandoned
Array ( [id] => 12256721 [patent_doc_number] => 09928871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Storage device and a method for defect scanning of the same' [patent_app_type] => utility [patent_app_number] => 15/060542 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7119 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060542 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060542
Storage device and a method for defect scanning of the same Mar 2, 2016 Issued
Array ( [id] => 11531046 [patent_doc_number] => 20170091025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'MEMORY SYSTEM AND METHOD FOR ERROR CORRECTION OF MEMORY' [patent_app_type] => utility [patent_app_number] => 15/059102 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4586 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059102 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059102
Memory system and method for error correction of memory Mar 1, 2016 Issued
Array ( [id] => 14254075 [patent_doc_number] => 10277250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Transmitter and parity permutation method thereof [patent_app_type] => utility [patent_app_number] => 15/058242 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 31735 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/058242
Transmitter and parity permutation method thereof Mar 1, 2016 Issued
Array ( [id] => 14708791 [patent_doc_number] => 10382165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Transmitter and shortening method thereof [patent_app_type] => utility [patent_app_number] => 15/058515 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 29214 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058515 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/058515
Transmitter and shortening method thereof Mar 1, 2016 Issued
Array ( [id] => 15476653 [patent_doc_number] => 10554222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Transmitter and parity permutation method thereof [patent_app_type] => utility [patent_app_number] => 15/058348 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 32584 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058348 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/058348
Transmitter and parity permutation method thereof Mar 1, 2016 Issued
Array ( [id] => 11791582 [patent_doc_number] => 09401222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-26 [patent_title] => 'Determining categories for memory fail conditions' [patent_app_type] => utility [patent_app_number] => 14/948743 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 14013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948743 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948743
Determining categories for memory fail conditions Nov 22, 2015 Issued
Array ( [id] => 11608951 [patent_doc_number] => 20170126256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'DYNAMIC CLIENT-SIDE SELECTION OF FEC INFORMATION' [patent_app_type] => utility [patent_app_number] => 14/930543 [patent_app_country] => US [patent_app_date] => 2015-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11690 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14930543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/930543
Dynamic client-side selection of FEC information Nov 1, 2015 Issued
Array ( [id] => 12173840 [patent_doc_number] => 09891985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => '256-bit parallel parser and checksum circuit with 1-hot state information bus' [patent_app_type] => utility [patent_app_number] => 14/929275 [patent_app_country] => US [patent_app_date] => 2015-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 133 [patent_figures_cnt] => 136 [patent_no_of_words] => 7654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14929275 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/929275
256-bit parallel parser and checksum circuit with 1-hot state information bus Oct 30, 2015 Issued
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