Austin Murata

Array ( [id] => 10715743 [patent_doc_number] => 20160061890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'INTEGRATED CIRCUIT DEVICE AND METHOD OF PERFORMING SELF-TESTING WITHIN AN INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 14/468917 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8564 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11816092 [patent_doc_number] => 09720036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Signal tracing using on-chip memory for in-system post-fabrication debug' [patent_app_type] => utility [patent_app_number] => 14/461528 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 9254 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14461528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10250034 [patent_doc_number] => 20150135030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'SPEEDING UP DEFECT DIAGNOSIS TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 14/462299 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 16192 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14462299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10337286 [patent_doc_number] => 20150222291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-06 [patent_title] => 'MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/453903 [patent_app_country] => US [patent_app_date] => 2014-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5992 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14453903 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10204339 [patent_doc_number] => 20150089327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/444856 [patent_app_country] => US [patent_app_date] => 2014-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14444856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11636947 [patent_doc_number] => 09658921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Maximal transition hamming codes' [patent_app_type] => utility [patent_app_number] => 14/338109 [patent_app_country] => US [patent_app_date] => 2014-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5071 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14338109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10493786 [patent_doc_number] => 20150378808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'Techniques for Handling Errors in Persistent Memory' [patent_app_type] => utility [patent_app_number] => 14/319387 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13792 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319387 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11510961 [patent_doc_number] => 09602134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Operating method of error correction code decoder and memory controller including the error correction code decoder' [patent_app_type] => utility [patent_app_number] => 14/314774 [patent_app_country] => US [patent_app_date] => 2014-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7352 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14314774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9784686 [patent_doc_number] => 20140301506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/310878 [patent_app_country] => US [patent_app_date] => 2014-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7819 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14310878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10485617 [patent_doc_number] => 20150370636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'CONSECUTIVE BIT ERROR DETECTION AND CORRECTION' [patent_app_type] => utility [patent_app_number] => 14/308107 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14308107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9787741 [patent_doc_number] => 20140304561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'SHARED FUSE WRAPPER ARCHITECTURE FOR MEMORY REPAIR' [patent_app_type] => utility [patent_app_number] => 14/305975 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5290 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9891657 [patent_doc_number] => 08977931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'Method and apparatus for nested dispersed storage' [patent_app_type] => utility [patent_app_number] => 14/287340 [patent_app_country] => US [patent_app_date] => 2014-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 12484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14287340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9700663 [patent_doc_number] => 20140250348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-04 [patent_title] => 'Controller and Method for Interfacing Between a Host Controller in a Host and a Flash Memory Device' [patent_app_type] => utility [patent_app_number] => 14/278672 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 20022 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14278672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10962811 [patent_doc_number] => 20140365841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'SIGNAL PROCESSING SYSTEM WITH BIST FUNCTION, TESTING METHOD THEREOF AND TESTING SIGNAL GENERATOR' [patent_app_type] => utility [patent_app_number] => 14/273985 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3435 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9645131 [patent_doc_number] => 20140223244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'FLASH STORAGE DEVICE WITH READ DISTURB MITIGATION' [patent_app_type] => utility [patent_app_number] => 14/257978 [patent_app_country] => US [patent_app_date] => 2014-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4429 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14257978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9658790 [patent_doc_number] => 20140229795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS' [patent_app_type] => utility [patent_app_number] => 14/254530 [patent_app_country] => US [patent_app_date] => 2014-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3110 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14254530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11917315 [patent_doc_number] => 09785501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Error detection and handling for a data storage device' [patent_app_type] => utility [patent_app_number] => 14/182567 [patent_app_country] => US [patent_app_date] => 2014-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12699 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14182567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10351719 [patent_doc_number] => 20150236724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'Dynamically Controlling Erasure Code Distribution In An Object Store' [patent_app_type] => utility [patent_app_number] => 14/183310 [patent_app_country] => US [patent_app_date] => 2014-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7964 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14183310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10047193 [patent_doc_number] => 09087591 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-21 [patent_title] => 'Method and apparatus for detecting valid data using selective modification of cyclic redundancy codes' [patent_app_type] => utility [patent_app_number] => 14/177063 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 12440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14177063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9866746 [patent_doc_number] => 20150046766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/386868 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 124 [patent_figures_cnt] => 124 [patent_no_of_words] => 53745 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14386868 [rel_patent_id] =>[rel_patent_doc_number] =>)