Austin Murata

Array ( [id] => 10928080 [patent_doc_number] => 20140331101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF WRITING DATA IN THE SAME' [patent_app_type] => utility [patent_app_number] => 14/160614 [patent_app_country] => US [patent_app_date] => 2014-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12560 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14160614 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10320661 [patent_doc_number] => 20150205665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'ECC METHOD FOR FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 14/158613 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10309200 [patent_doc_number] => 20150194201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'REAL TIME CORRECTION OF BIT FAILURE IN RESISTIVE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/150559 [patent_app_country] => US [patent_app_date] => 2014-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7320 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14150559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10300285 [patent_doc_number] => 20150185285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SYSTEM AND METHOD FOR REDUCED PIN LOGIC SCANNING' [patent_app_type] => utility [patent_app_number] => 14/143821 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11686511 [patent_doc_number] => 09684558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Accessing data stored in a dispersed storage memory' [patent_app_type] => utility [patent_app_number] => 14/107157 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 14489 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9800847 [patent_doc_number] => 20150012791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'PARALLEL TEST DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/074820 [patent_app_country] => US [patent_app_date] => 2013-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6509 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074820 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9800848 [patent_doc_number] => 20150012792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING A TRANSMISSION CONTROL PROTOCOL MINIMUM RETRANSMISSION TIMER' [patent_app_type] => utility [patent_app_number] => 14/061259 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9604923 [patent_doc_number] => 20140201605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'SIGNAL RECEPTION APPARATUS, BLOCK DECODING UNIT AND METHOD THEREOF IN RADIO COMMUNICATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/061142 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5540 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10228354 [patent_doc_number] => 20150113348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-23 [patent_title] => 'IMPLEMENTING MISR COMPRESSION METHODS FOR TEST TIME REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/060744 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3634 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14060744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11412404 [patent_doc_number] => 09559725 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-31 [patent_title] => 'Multi-strength reed-solomon outer code protection' [patent_app_type] => utility [patent_app_number] => 14/061344 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4285 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9451780 [patent_doc_number] => 20140122950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 14/059796 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8085 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9814594 [patent_doc_number] => 20150026540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'FLASH DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/059615 [patent_app_country] => US [patent_app_date] => 2013-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3109 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14059615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11286281 [patent_doc_number] => 09502139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-22 [patent_title] => 'Fine grained online remapping to handle memory errors' [patent_app_type] => utility [patent_app_number] => 14/058919 [patent_app_country] => US [patent_app_date] => 2013-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14058919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10046060 [patent_doc_number] => 09086454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Timing-aware test generation and fault simulation' [patent_app_type] => utility [patent_app_number] => 14/053322 [patent_app_country] => US [patent_app_date] => 2013-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 16486 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14053322 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11451486 [patent_doc_number] => 09575125 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-21 [patent_title] => 'Memory device with reduced test time' [patent_app_type] => utility [patent_app_number] => 14/049543 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14049543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11788211 [patent_doc_number] => 09397706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-19 [patent_title] => 'System and method for irregular multiple dimension decoding and encoding' [patent_app_type] => utility [patent_app_number] => 14/049547 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16214 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14049547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11576888 [patent_doc_number] => 09632139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'IO pad circuitry with safety monitoring and control for integrated circuits' [patent_app_type] => utility [patent_app_number] => 14/050077 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3190 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12166987 [patent_doc_number] => 09885753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Scan systems and methods' [patent_app_type] => utility [patent_app_number] => 14/050242 [patent_app_country] => US [patent_app_date] => 2013-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7441 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14050242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9282259 [patent_doc_number] => 20140032227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'BIT ERROR MANAGEMENT METHODS FOR WIRELESS AUDIO COMMUNICATION CHANNELS' [patent_app_type] => utility [patent_app_number] => 14/042228 [patent_app_country] => US [patent_app_date] => 2013-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14042228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9341578 [patent_doc_number] => 20140068362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES' [patent_app_type] => utility [patent_app_number] => 14/033536 [patent_app_country] => US [patent_app_date] => 2013-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6723 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14033536 [rel_patent_id] =>[rel_patent_doc_number] =>)