Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8588723 [patent_doc_number] => 20130007544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'MAPPING OF RANDOM DEFECTS IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/175801 [patent_app_country] => US [patent_app_date] => 2011-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6502 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13175801 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/175801
Mapping of random defects in a memory device Jun 30, 2011 Issued
Array ( [id] => 7665086 [patent_doc_number] => 20110314355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'ACCESSING DATA STORED IN A DISPERSED STORAGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/154167 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14388 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13154167 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154167
Accessing data stored in a dispersed storage memory Jun 5, 2011 Issued
Array ( [id] => 7665087 [patent_doc_number] => 20110314356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'VERIFYING INTEGRITY OF DATA STORED IN A DISPERSED STORAGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/154181 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14388 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13154181 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/154181
Verifying integrity of data stored in a dispersed storage memory Jun 5, 2011 Issued
Array ( [id] => 9029729 [patent_doc_number] => 08539327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Semiconductor integrated circuit for testing logic circuit' [patent_app_type] => utility [patent_app_number] => 13/153681 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2482 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13153681 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/153681
Semiconductor integrated circuit for testing logic circuit Jun 5, 2011 Issued
Array ( [id] => 8574841 [patent_doc_number] => 08341503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Methods and systems for storing data in memory using zoning' [patent_app_type] => utility [patent_app_number] => 13/151000 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2635 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13151000 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/151000
Methods and systems for storing data in memory using zoning May 31, 2011 Issued
Array ( [id] => 8479264 [patent_doc_number] => 20120278671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'CIRCUIT AND METHOD FOR DIAGNOSING SCAN CHAIN FAILURES' [patent_app_type] => utility [patent_app_number] => 13/093942 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6686 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13093942 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093942
Circuit and method for diagnosing scan chain failures Apr 25, 2011 Issued
Array ( [id] => 8479271 [patent_doc_number] => 20120278679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'Iterating Inner and Outer Codes for Data Recovery' [patent_app_type] => utility [patent_app_number] => 13/094048 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13094048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/094048
Iterating inner and outer codes for data recovery Apr 25, 2011 Issued
Array ( [id] => 7714291 [patent_doc_number] => 20120005545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'Computer product, verification support apparatus, and verification support method' [patent_app_type] => utility [patent_app_number] => 13/064902 [patent_app_country] => US [patent_app_date] => 2011-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13140 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005545.pdf [firstpage_image] =>[orig_patent_app_number] => 13064902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/064902
Verification support of circuit blocks having independent clock domains Apr 24, 2011 Issued
Array ( [id] => 8952809 [patent_doc_number] => 20130198590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'METHOD OF REDUCING PEAK-TO-AVERAGE POWER RATIO, CUBIC METRIC AND BLOCK ERROR RATE IN OFDM SYSTEMS USING NETWORK CODING' [patent_app_type] => utility [patent_app_number] => 13/642423 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7497 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13642423 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/642423
Method of reducing peak-to-average power ratio, cubic metric and block error rate in OFDM systems using network coding Apr 20, 2011 Issued
Array ( [id] => 6210860 [patent_doc_number] => 20110134707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'BLOCK ISOLATION CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/024169 [patent_app_country] => US [patent_app_date] => 2011-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5312 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20110134707.pdf [firstpage_image] =>[orig_patent_app_number] => 13024169 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024169
BLOCK ISOLATION CONTROL CIRCUIT Feb 8, 2011 Abandoned
Array ( [id] => 6006213 [patent_doc_number] => 20110119542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'SEMICONDUCTOR DEVICE TEST SYSTEM WITH TEST INTERFACE MEANS' [patent_app_type] => utility [patent_app_number] => 13/008517 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7482 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119542.pdf [firstpage_image] =>[orig_patent_app_number] => 13008517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008517
Semiconductor device test system with test interface means Jan 17, 2011 Issued
Array ( [id] => 8280049 [patent_doc_number] => 20120173921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'REDUNDANCY MEMORY STORAGE SYSTEM AND A METHOD FOR CONTROLLING A REDUNDANCY MEMORY STORAGE SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/985139 [patent_app_country] => US [patent_app_date] => 2011-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12985139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985139
REDUNDANCY MEMORY STORAGE SYSTEM AND A METHOD FOR CONTROLLING A REDUNDANCY MEMORY STORAGE SYSTEM Jan 4, 2011 Abandoned
Array ( [id] => 9102774 [patent_doc_number] => 08566668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'Edge memory architecture for LDPC decoder' [patent_app_type] => utility [patent_app_number] => 12/984013 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8670 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984013 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984013
Edge memory architecture for LDPC decoder Jan 3, 2011 Issued
Array ( [id] => 6153941 [patent_doc_number] => 20110022914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Replacement messages for identifying and preventing errors during the transmission of realtime-critical data' [patent_app_type] => utility [patent_app_number] => 12/898770 [patent_app_country] => US [patent_app_date] => 2010-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2475 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022914.pdf [firstpage_image] =>[orig_patent_app_number] => 12898770 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/898770
Replacement messages for identifying and preventing errors during the transmission of realtime-critical data Oct 5, 2010 Issued
Array ( [id] => 8303192 [patent_doc_number] => 20120185751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-19 [patent_title] => 'SERIAL PROCESSING METHOD, PARALLEL PROCESSING METHOD OF BIT RATE MATCHING AND DEVICE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/393298 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8724 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13393298 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/393298
Serial processing method, parallel processing method of bit rate matching and device thereof Sep 27, 2010 Issued
Array ( [id] => 6133065 [patent_doc_number] => 20110007539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'TEST MODE FOR MULTI-CHIP INTEGRATED CIRCUIT PACKAGES' [patent_app_type] => utility [patent_app_number] => 12/885781 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4615 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20110007539.pdf [firstpage_image] =>[orig_patent_app_number] => 12885781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/885781
Test mode for multi-chip integrated circuit packages Sep 19, 2010 Issued
Array ( [id] => 8280070 [patent_doc_number] => 20120173949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'METHOD OF CONSTRUCTING PARITY-CHECK MATRIX OF LDPC CODE AND ENCODING METHOD AND ENCODING APPARATUS BASED ON THE METHOD' [patent_app_type] => utility [patent_app_number] => 13/395478 [patent_app_country] => US [patent_app_date] => 2010-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5751 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13395478 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/395478
METHOD OF CONSTRUCTING PARITY-CHECK MATRIX OF LDPC CODE AND ENCODING METHOD AND ENCODING APPARATUS BASED ON THE METHOD Aug 10, 2010 Abandoned
Array ( [id] => 6154016 [patent_doc_number] => 20110022929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Error correcting apparatus, method of controlling memory of error correcting apparatus, and optical disc recording/reproducing apparatus' [patent_app_type] => utility [patent_app_number] => 12/801996 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16160 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022929.pdf [firstpage_image] =>[orig_patent_app_number] => 12801996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/801996
Error correcting apparatus, method of controlling memory of error correcting apparatus, and optical disc recording/reproducing apparatus Jul 6, 2010 Abandoned
Array ( [id] => 6198073 [patent_doc_number] => 20110029831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'METHOD OF TRANSMITTING AND RECEIVING ARQ FEEDBACK INFORMATION' [patent_app_type] => utility [patent_app_number] => 12/830996 [patent_app_country] => US [patent_app_date] => 2010-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7700 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20110029831.pdf [firstpage_image] =>[orig_patent_app_number] => 12830996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/830996
Method of transmitting and receiving ARQ feedback information Jul 5, 2010 Issued
Array ( [id] => 9507130 [patent_doc_number] => 08745460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Encoding/decoding apparatus and method' [patent_app_type] => utility [patent_app_number] => 12/803703 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12803703 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/803703
Encoding/decoding apparatus and method Jul 1, 2010 Issued
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