Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7768321 [patent_doc_number] => 08117508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Non-volatile memory device and programming method thereof' [patent_app_type] => utility [patent_app_number] => 12/650006 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7682 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117508.pdf [firstpage_image] =>[orig_patent_app_number] => 12650006 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650006
Non-volatile memory device and programming method thereof Dec 29, 2009 Issued
Array ( [id] => 8594964 [patent_doc_number] => 08352847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Matrix vector multiplication for error-correction encoding and the like' [patent_app_type] => utility [patent_app_number] => 12/644161 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12644161 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/644161
Matrix vector multiplication for error-correction encoding and the like Dec 21, 2009 Issued
Array ( [id] => 9251901 [patent_doc_number] => 08615692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-24 [patent_title] => 'Method and system for analyzing test vectors to determine toggle counts' [patent_app_type] => utility [patent_app_number] => 12/637935 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7654 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12637935 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/637935
Method and system for analyzing test vectors to determine toggle counts Dec 14, 2009 Issued
Array ( [id] => 6449920 [patent_doc_number] => 20100153800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'LOGIC TESTER AND METHOD FOR SIMULTANEOUSLY MEASURING DELAY PERIODS OF MULTIPLE TESTED DEVICES' [patent_app_type] => utility [patent_app_number] => 12/638368 [patent_app_country] => US [patent_app_date] => 2009-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2582 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153800.pdf [firstpage_image] =>[orig_patent_app_number] => 12638368 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/638368
Logic tester and method for simultaneously measuring delay periods of multiple tested devices Dec 14, 2009 Issued
Array ( [id] => 6449887 [patent_doc_number] => 20100153797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Apparatus and method of authenticating Joint Test Action Group (JTAG)' [patent_app_type] => utility [patent_app_number] => 12/653082 [patent_app_country] => US [patent_app_date] => 2009-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3552 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20100153797.pdf [firstpage_image] =>[orig_patent_app_number] => 12653082 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/653082
Apparatus and method of authenticating joint test action group (JTAG) Dec 7, 2009 Issued
Array ( [id] => 7547977 [patent_doc_number] => 08055958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Replacement data storage circuit storing address of defective memory cell' [patent_app_type] => utility [patent_app_number] => 12/630094 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7061 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/055/08055958.pdf [firstpage_image] =>[orig_patent_app_number] => 12630094 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630094
Replacement data storage circuit storing address of defective memory cell Dec 2, 2009 Issued
Array ( [id] => 6388702 [patent_doc_number] => 20100083074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Block Code Decoding Method And Device Thereof' [patent_app_type] => utility [patent_app_number] => 12/567558 [patent_app_country] => US [patent_app_date] => 2009-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5270 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083074.pdf [firstpage_image] =>[orig_patent_app_number] => 12567558 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/567558
Block code decoding method and device thereof Sep 24, 2009 Issued
Array ( [id] => 5981917 [patent_doc_number] => 20110072333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'CONTROL METHOD FOR FLASH MEMORY BASED ON VARIABLE LENGTH ECC' [patent_app_type] => utility [patent_app_number] => 12/566627 [patent_app_country] => US [patent_app_date] => 2009-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20110072333.pdf [firstpage_image] =>[orig_patent_app_number] => 12566627 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/566627
CONTROL METHOD FOR FLASH MEMORY BASED ON VARIABLE LENGTH ECC Sep 23, 2009 Abandoned
Array ( [id] => 6204124 [patent_doc_number] => 20110066910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'STEALTH MESSAGE TRANSMISSION IN A NETWORK' [patent_app_type] => utility [patent_app_number] => 12/560665 [patent_app_country] => US [patent_app_date] => 2009-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066910.pdf [firstpage_image] =>[orig_patent_app_number] => 12560665 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/560665
Stealth message transmission in a network Sep 15, 2009 Issued
Array ( [id] => 6302403 [patent_doc_number] => 20100162055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'MEMORY SYSTEM, TRANSFER CONTROLLER, AND MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/558718 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7410 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20100162055.pdf [firstpage_image] =>[orig_patent_app_number] => 12558718 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558718
MEMORY SYSTEM, TRANSFER CONTROLLER, AND MEMORY CONTROL METHOD Sep 13, 2009 Abandoned
Array ( [id] => 6204120 [patent_doc_number] => 20110066906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'Pulse Triggered Latches with Scan Functionality' [patent_app_type] => utility [patent_app_number] => 12/558754 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5023 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20110066906.pdf [firstpage_image] =>[orig_patent_app_number] => 12558754 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558754
Pulse Triggered Latches with Scan Functionality Sep 13, 2009 Abandoned
Array ( [id] => 8593412 [patent_doc_number] => 08351290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-08 [patent_title] => 'Erased page detection' [patent_app_type] => utility [patent_app_number] => 12/557311 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 12447 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12557311 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557311
Erased page detection Sep 9, 2009 Issued
Array ( [id] => 8716202 [patent_doc_number] => 08402353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Cyclic code processing circuit, network interface card, and cyclic code processing method' [patent_app_type] => utility [patent_app_number] => 12/557269 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 20779 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12557269 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/557269
Cyclic code processing circuit, network interface card, and cyclic code processing method Sep 9, 2009 Issued
Array ( [id] => 6387423 [patent_doc_number] => 20100082875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'TRANSFER DEVICE' [patent_app_type] => utility [patent_app_number] => 12/556785 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8402 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20100082875.pdf [firstpage_image] =>[orig_patent_app_number] => 12556785 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556785
TRANSFER DEVICE Sep 9, 2009 Abandoned
Array ( [id] => 6312812 [patent_doc_number] => 20100070827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'ERROR CORRECTION CIRCUIT, FLASH MEMORY SYSTEM INCLUDING THE ERROR CORRECTION CIRCUIT, AND OPERATING METHOD OF THE ERROR CORRECTION CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/556822 [patent_app_country] => US [patent_app_date] => 2009-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5382 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20100070827.pdf [firstpage_image] =>[orig_patent_app_number] => 12556822 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556822
Error correction circuit, flash memory system including the error correction circuit, and operating method of the error correction circuit Sep 9, 2009 Issued
Array ( [id] => 6253288 [patent_doc_number] => 20100138709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'METHOD AND APPARATUS FOR DELAY FAULT COVERAGE ENHANCEMENT' [patent_app_type] => utility [patent_app_number] => 12/554437 [patent_app_country] => US [patent_app_date] => 2009-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20100138709.pdf [firstpage_image] =>[orig_patent_app_number] => 12554437 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/554437
METHOD AND APPARATUS FOR DELAY FAULT COVERAGE ENHANCEMENT Sep 3, 2009 Abandoned
Array ( [id] => 5932678 [patent_doc_number] => 20110041005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-17 [patent_title] => 'Controller and Method for Providing Read Status and Spare Block Management Information in a Flash Memory System' [patent_app_type] => utility [patent_app_number] => 12/539379 [patent_app_country] => US [patent_app_date] => 2009-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 20053 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20110041005.pdf [firstpage_image] =>[orig_patent_app_number] => 12539379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/539379
Controller and Method for Providing Read Status and Spare Block Management Information in a Flash Memory System Aug 10, 2009 Abandoned
Array ( [id] => 10073284 [patent_doc_number] => 09111645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-18 [patent_title] => 'Request-command encoding for reduced-data-rate testing' [patent_app_type] => utility [patent_app_number] => 13/000280 [patent_app_country] => US [patent_app_date] => 2009-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4583 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13000280 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/000280
Request-command encoding for reduced-data-rate testing Jul 16, 2009 Issued
Array ( [id] => 7680991 [patent_doc_number] => 20100023817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'TEST SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/499977 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3643 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023817.pdf [firstpage_image] =>[orig_patent_app_number] => 12499977 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499977
TEST SYSTEM AND METHOD Jul 8, 2009 Abandoned
Array ( [id] => 6652032 [patent_doc_number] => 20100229058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'METHOD AND APPARATUS FOR SYSTEM TESTING USING SCAN CHAIN DECOMPOSITION' [patent_app_type] => utility [patent_app_number] => 12/495336 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 27084 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229058.pdf [firstpage_image] =>[orig_patent_app_number] => 12495336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495336
METHOD AND APPARATUS FOR SYSTEM TESTING USING SCAN CHAIN DECOMPOSITION Jun 29, 2009 Abandoned
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