
Austin Murata
Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )
| Most Active Art Unit | 1712 |
| Art Unit(s) | 1712, 1792 |
| Total Applications | 853 |
| Issued Applications | 467 |
| Pending Applications | 93 |
| Abandoned Applications | 315 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6363425
[patent_doc_number] => 20100332894
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-30
[patent_title] => 'BIT ERROR THRESHOLD AND REMAPPING A MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/494904
[patent_app_country] => US
[patent_app_date] => 2009-06-30
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[pdf_file] => publications/A1/0332/20100332894.pdf
[firstpage_image] =>[orig_patent_app_number] => 12494904
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/494904 | BIT ERROR THRESHOLD AND REMAPPING A MEMORY DEVICE | Jun 29, 2009 | Abandoned |
Array
(
[id] => 5497560
[patent_doc_number] => 20090265588
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-22
[patent_title] => 'SYSTEM AND METHOD FOR RUNNING TEST AND REDUNDANCY ANALYSIS IN PARALLEL'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2009-06-24
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[pdf_file] => publications/A1/0265/20090265588.pdf
[firstpage_image] =>[orig_patent_app_number] => 12490657
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/490657 | System and method for running test and redundancy analysis in parallel | Jun 23, 2009 | Issued |
Array
(
[id] => 5375950
[patent_doc_number] => 20090313511
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-17
[patent_title] => 'SEMICONDUCTOR DEVICE TESTING'
[patent_app_type] => utility
[patent_app_number] => 12/484647
[patent_app_country] => US
[patent_app_date] => 2009-06-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/484647 | Semiconductor device testing | Jun 14, 2009 | Issued |
Array
(
[id] => 6644367
[patent_doc_number] => 20100313092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-09
[patent_title] => 'TECHNIQUE FOR INITIALIZING DATA AND INSTRUCTIONS FOR CORE FUNCTIONAL PATTERN GENERATION IN MULTI-CORE PROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 12/479535
[patent_app_country] => US
[patent_app_date] => 2009-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[firstpage_image] =>[orig_patent_app_number] => 12479535
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/479535 | Technique for initializing data and instructions for core functional pattern generation in multi-core processor | Jun 4, 2009 | Issued |
Array
(
[id] => 5317700
[patent_doc_number] => 20090282298
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[patent_kind] => A1
[patent_issue_date] => 2009-11-12
[patent_title] => 'BIT ERROR MANAGEMENT METHODS FOR WIRELESS AUDIO COMMUNICATION CHANNELS'
[patent_app_type] => utility
[patent_app_number] => 12/431184
[patent_app_country] => US
[patent_app_date] => 2009-04-28
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[pdf_file] => publications/A1/0282/20090282298.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/431184 | Bit error management methods for wireless audio communication channels | Apr 27, 2009 | Issued |
Array
(
[id] => 5497564
[patent_doc_number] => 20090265592
[patent_country] => US
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[patent_issue_date] => 2009-10-22
[patent_title] => 'MEMORY DEVICE AND TEST METHOD THEREOF'
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[firstpage_image] =>[orig_patent_app_number] => 12423343
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/423343 | MEMORY DEVICE AND TEST METHOD THEREOF | Apr 13, 2009 | Abandoned |
Array
(
[id] => 5956908
[patent_doc_number] => 20110035638
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'Timing Failure Debug'
[patent_app_type] => utility
[patent_app_number] => 12/420047
[patent_app_country] => US
[patent_app_date] => 2009-04-07
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[firstpage_image] =>[orig_patent_app_number] => 12420047
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/420047 | Timing Failure Debug | Apr 6, 2009 | Abandoned |
Array
(
[id] => 6117210
[patent_doc_number] => 20110191646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-04
[patent_title] => 'Fault-and Variation-Tolerant Energy - and Area-Efficient Links for Network-on-Chips'
[patent_app_type] => utility
[patent_app_number] => 12/922948
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/922948 | Fault-and Variation-Tolerant Energy - and Area-Efficient Links for Network-on-Chips | Apr 5, 2009 | Abandoned |
Array
(
[id] => 7679583
[patent_doc_number] => 20100107004
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[patent_kind] => A1
[patent_issue_date] => 2010-04-29
[patent_title] => 'METHOD FOR SELECTIVELY RETRIEVING COLUMN REDUNDANCY DATA IN MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/414935
[patent_app_country] => US
[patent_app_date] => 2009-03-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0107/20100107004.pdf
[firstpage_image] =>[orig_patent_app_number] => 12414935
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/414935 | Method for selectively retrieving column redundancy data in memory device | Mar 30, 2009 | Issued |
Array
(
[id] => 9102761
[patent_doc_number] => 08566655
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[patent_issue_date] => 2013-10-22
[patent_title] => 'Method for operating a communication system having a plurality of nodes, and a communication system therefor'
[patent_app_type] => utility
[patent_app_number] => 12/998110
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Array
(
[id] => 8183215
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[patent_issue_date] => 2012-05-15
[patent_title] => 'Memory testing using multiple processor unit, DMA, and SIMD instruction'
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Array
(
[id] => 6006222
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Array
(
[id] => 6553619
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/274547 | Uninitialized memory detection using error correction codes and built-in self test | Nov 19, 2008 | Issued |
Array
(
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[patent_title] => 'METHOD AND APPARATUS FOR TRACKING, REPORTING AND CORRECTING SINGLE-BIT MEMORY ERRORS'
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Array
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Array
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Array
(
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[patent_title] => 'LOW OVERHEAD INPUT AND OUTPUT BOUNDARY SCAN CELLS'
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Array
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Array
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Array
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