Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6363425 [patent_doc_number] => 20100332894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'BIT ERROR THRESHOLD AND REMAPPING A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/494904 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332894.pdf [firstpage_image] =>[orig_patent_app_number] => 12494904 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494904
BIT ERROR THRESHOLD AND REMAPPING A MEMORY DEVICE Jun 29, 2009 Abandoned
Array ( [id] => 5497560 [patent_doc_number] => 20090265588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'SYSTEM AND METHOD FOR RUNNING TEST AND REDUNDANCY ANALYSIS IN PARALLEL' [patent_app_type] => utility [patent_app_number] => 12/490657 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3663 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265588.pdf [firstpage_image] =>[orig_patent_app_number] => 12490657 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/490657
System and method for running test and redundancy analysis in parallel Jun 23, 2009 Issued
Array ( [id] => 5375950 [patent_doc_number] => 20090313511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'SEMICONDUCTOR DEVICE TESTING' [patent_app_type] => utility [patent_app_number] => 12/484647 [patent_app_country] => US [patent_app_date] => 2009-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4437 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20090313511.pdf [firstpage_image] =>[orig_patent_app_number] => 12484647 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/484647
Semiconductor device testing Jun 14, 2009 Issued
Array ( [id] => 6644367 [patent_doc_number] => 20100313092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'TECHNIQUE FOR INITIALIZING DATA AND INSTRUCTIONS FOR CORE FUNCTIONAL PATTERN GENERATION IN MULTI-CORE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/479535 [patent_app_country] => US [patent_app_date] => 2009-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20100313092.pdf [firstpage_image] =>[orig_patent_app_number] => 12479535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/479535
Technique for initializing data and instructions for core functional pattern generation in multi-core processor Jun 4, 2009 Issued
Array ( [id] => 5317700 [patent_doc_number] => 20090282298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'BIT ERROR MANAGEMENT METHODS FOR WIRELESS AUDIO COMMUNICATION CHANNELS' [patent_app_type] => utility [patent_app_number] => 12/431184 [patent_app_country] => US [patent_app_date] => 2009-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9696 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282298.pdf [firstpage_image] =>[orig_patent_app_number] => 12431184 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/431184
Bit error management methods for wireless audio communication channels Apr 27, 2009 Issued
Array ( [id] => 5497564 [patent_doc_number] => 20090265592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'MEMORY DEVICE AND TEST METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/423343 [patent_app_country] => US [patent_app_date] => 2009-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1792 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265592.pdf [firstpage_image] =>[orig_patent_app_number] => 12423343 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/423343
MEMORY DEVICE AND TEST METHOD THEREOF Apr 13, 2009 Abandoned
Array ( [id] => 5956908 [patent_doc_number] => 20110035638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'Timing Failure Debug' [patent_app_type] => utility [patent_app_number] => 12/420047 [patent_app_country] => US [patent_app_date] => 2009-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4931 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20110035638.pdf [firstpage_image] =>[orig_patent_app_number] => 12420047 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/420047
Timing Failure Debug Apr 6, 2009 Abandoned
Array ( [id] => 6117210 [patent_doc_number] => 20110191646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'Fault-and Variation-Tolerant Energy - and Area-Efficient Links for Network-on-Chips' [patent_app_type] => utility [patent_app_number] => 12/922948 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20110191646.pdf [firstpage_image] =>[orig_patent_app_number] => 12922948 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/922948
Fault-and Variation-Tolerant Energy - and Area-Efficient Links for Network-on-Chips Apr 5, 2009 Abandoned
Array ( [id] => 7679583 [patent_doc_number] => 20100107004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'METHOD FOR SELECTIVELY RETRIEVING COLUMN REDUNDANCY DATA IN MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/414935 [patent_app_country] => US [patent_app_date] => 2009-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20100107004.pdf [firstpage_image] =>[orig_patent_app_number] => 12414935 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/414935
Method for selectively retrieving column redundancy data in memory device Mar 30, 2009 Issued
Array ( [id] => 9102761 [patent_doc_number] => 08566655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Method for operating a communication system having a plurality of nodes, and a communication system therefor' [patent_app_type] => utility [patent_app_number] => 12/998110 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3856 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12998110 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/998110
Method for operating a communication system having a plurality of nodes, and a communication system therefor Mar 5, 2009 Issued
Array ( [id] => 8183215 [patent_doc_number] => 08181072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Memory testing using multiple processor unit, DMA, and SIMD instruction' [patent_app_type] => utility [patent_app_number] => 12/357080 [patent_app_country] => US [patent_app_date] => 2009-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7970 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 398 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/181/08181072.pdf [firstpage_image] =>[orig_patent_app_number] => 12357080 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/357080
Memory testing using multiple processor unit, DMA, and SIMD instruction Jan 20, 2009 Issued
Array ( [id] => 6006222 [patent_doc_number] => 20110119548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'RADIO TRANSMISSION DEVICE AND RETRANSMISSION CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 12/811671 [patent_app_country] => US [patent_app_date] => 2009-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6270 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119548.pdf [firstpage_image] =>[orig_patent_app_number] => 12811671 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/811671
RADIO TRANSMISSION DEVICE AND RETRANSMISSION CONTROL METHOD Jan 6, 2009 Abandoned
Array ( [id] => 6553619 [patent_doc_number] => 20100125765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'UNINITIALIZED MEMORY DETECTION USING ERROR CORRECTION CODES AND BUILT-IN SELF TEST' [patent_app_type] => utility [patent_app_number] => 12/274547 [patent_app_country] => US [patent_app_date] => 2008-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20100125765.pdf [firstpage_image] =>[orig_patent_app_number] => 12274547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/274547
Uninitialized memory detection using error correction codes and built-in self test Nov 19, 2008 Issued
Array ( [id] => 7686359 [patent_doc_number] => 20090177932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'METHOD AND APPARATUS FOR TRACKING, REPORTING AND CORRECTING SINGLE-BIT MEMORY ERRORS' [patent_app_type] => utility [patent_app_number] => 12/274044 [patent_app_country] => US [patent_app_date] => 2008-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16960 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20090177932.pdf [firstpage_image] =>[orig_patent_app_number] => 12274044 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/274044
Method and apparatus for tracking, reporting and correcting single-bit memory errors Nov 18, 2008 Issued
Array ( [id] => 5273656 [patent_doc_number] => 20090077432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Semiconductor Memory Device' [patent_app_type] => utility [patent_app_number] => 12/273270 [patent_app_country] => US [patent_app_date] => 2008-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5529 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077432.pdf [firstpage_image] =>[orig_patent_app_number] => 12273270 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/273270
Semiconductor Memory Device Nov 17, 2008 Abandoned
Array ( [id] => 5424274 [patent_doc_number] => 20090150730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'Test apparatus for data storage device and test method for data storage device' [patent_app_type] => utility [patent_app_number] => 12/291861 [patent_app_country] => US [patent_app_date] => 2008-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5281 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150730.pdf [firstpage_image] =>[orig_patent_app_number] => 12291861 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/291861
Test apparatus for data storage device and test method for data storage device Nov 13, 2008 Abandoned
Array ( [id] => 5362991 [patent_doc_number] => 20090037785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'LOW OVERHEAD INPUT AND OUTPUT BOUNDARY SCAN CELLS' [patent_app_type] => utility [patent_app_number] => 12/251587 [patent_app_country] => US [patent_app_date] => 2008-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10331 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20090037785.pdf [firstpage_image] =>[orig_patent_app_number] => 12251587 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/251587
Three boundary scan cell switches controlling input to output buffer Oct 14, 2008 Issued
Array ( [id] => 8120289 [patent_doc_number] => 08161367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Correction of single event upset error within sequential storage circuitry of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/285517 [patent_app_country] => US [patent_app_date] => 2008-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7967 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161367.pdf [firstpage_image] =>[orig_patent_app_number] => 12285517 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/285517
Correction of single event upset error within sequential storage circuitry of an integrated circuit Oct 6, 2008 Issued
Array ( [id] => 9128990 [patent_doc_number] => 08576946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Method and system for cooperative communications with minimal coordination' [patent_app_type] => utility [patent_app_number] => 12/245993 [patent_app_country] => US [patent_app_date] => 2008-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8910 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12245993 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/245993
Method and system for cooperative communications with minimal coordination Oct 5, 2008 Issued
Array ( [id] => 5571415 [patent_doc_number] => 20090254794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'METHOD FOR EFFICIENT PACKET FRAMING IN A COMMUNICATION NETWORK' [patent_app_type] => utility [patent_app_number] => 12/245535 [patent_app_country] => US [patent_app_date] => 2008-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7707 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20090254794.pdf [firstpage_image] =>[orig_patent_app_number] => 12245535 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/245535
METHOD FOR EFFICIENT PACKET FRAMING IN A COMMUNICATION NETWORK Oct 2, 2008 Abandoned
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