Search

Austin Murata

Examiner (ID: 3702, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1792, 1712
Total Applications
876
Issued Applications
483
Pending Applications
87
Abandoned Applications
318

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10500567 [patent_doc_number] => 09228964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'System for aligning patterns on a substrate' [patent_app_type] => utility [patent_app_number] => 14/230114 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 16431 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230114 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230114
System for aligning patterns on a substrate Mar 30, 2014 Issued
Array ( [id] => 11847672 [patent_doc_number] => 09735231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Block layer in the metal gate of MOS devices' [patent_app_type] => utility [patent_app_number] => 14/231099 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14231099 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/231099
Block layer in the metal gate of MOS devices Mar 30, 2014 Issued
Array ( [id] => 11725373 [patent_doc_number] => 09698240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Semiconductor device and formation thereof' [patent_app_type] => utility [patent_app_number] => 14/230203 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 4310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230203 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230203
Semiconductor device and formation thereof Mar 30, 2014 Issued
Array ( [id] => 10568425 [patent_doc_number] => 09291587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Method for forming aligned patterns on a substrate' [patent_app_type] => utility [patent_app_number] => 14/230127 [patent_app_country] => US [patent_app_date] => 2014-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 16431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14230127 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/230127
Method for forming aligned patterns on a substrate Mar 30, 2014 Issued
Array ( [id] => 10394711 [patent_doc_number] => 20150279718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Heat Assisted Handling of Highly Warped Substrates Post Temporary Bonding' [patent_app_type] => utility [patent_app_number] => 14/229902 [patent_app_country] => US [patent_app_date] => 2014-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16601 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14229902 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/229902
Heat assisted handling of highly warped substrates post temporary bonding Mar 28, 2014 Issued
Array ( [id] => 10617859 [patent_doc_number] => 09337311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-10 [patent_title] => 'Electronic component, a semiconductor wafer and a method for producing an electronic component' [patent_app_type] => utility [patent_app_number] => 14/225652 [patent_app_country] => US [patent_app_date] => 2014-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2565 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14225652 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/225652
Electronic component, a semiconductor wafer and a method for producing an electronic component Mar 25, 2014 Issued
Array ( [id] => 11453209 [patent_doc_number] => 09576860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Method and apparatus providing inline photoluminescence analysis of a photovoltaic device' [patent_app_type] => utility [patent_app_number] => 14/205810 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5252 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205810 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/205810
Method and apparatus providing inline photoluminescence analysis of a photovoltaic device Mar 11, 2014 Issued
Array ( [id] => 11252997 [patent_doc_number] => 09478509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Mechanically anchored backside C4 pad' [patent_app_type] => utility [patent_app_number] => 14/198711 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5362 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198711
Mechanically anchored backside C4 pad Mar 5, 2014 Issued
Array ( [id] => 10370618 [patent_doc_number] => 20150255623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'VTFT WITH POST, CAP, AND ALIGNED GATE' [patent_app_type] => utility [patent_app_number] => 14/198633 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 20002 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198633 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198633
VTFT with post, cap, and aligned gate Mar 5, 2014 Issued
Array ( [id] => 10370576 [patent_doc_number] => 20150255581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'Semiconductor Devices and Methods of Manufacture Thereof' [patent_app_type] => utility [patent_app_number] => 14/199595 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14199595 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/199595
Semiconductor devices and methods of manufacture thereof Mar 5, 2014 Issued
Array ( [id] => 10145214 [patent_doc_number] => 09178029 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Forming a VTFT gate using printing' [patent_app_type] => utility [patent_app_number] => 14/198677 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 73 [patent_no_of_words] => 19918 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198677 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198677
Forming a VTFT gate using printing Mar 5, 2014 Issued
Array ( [id] => 10590516 [patent_doc_number] => 09312136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Replacement metal gate stack for diffusion prevention' [patent_app_type] => utility [patent_app_number] => 14/199045 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5313 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14199045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/199045
Replacement metal gate stack for diffusion prevention Mar 5, 2014 Issued
Array ( [id] => 10053585 [patent_doc_number] => 09093470 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-28 [patent_title] => 'VTFT formation using capillary action' [patent_app_type] => utility [patent_app_number] => 14/198621 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 65 [patent_no_of_words] => 16710 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198621 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198621
VTFT formation using capillary action Mar 5, 2014 Issued
Array ( [id] => 10601507 [patent_doc_number] => 09322061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Nanochannel device with three dimensional gradient by single step etching for molecular detection' [patent_app_type] => utility [patent_app_number] => 14/199248 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 7596 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14199248 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/199248
Nanochannel device with three dimensional gradient by single step etching for molecular detection Mar 5, 2014 Issued
Array ( [id] => 10184877 [patent_doc_number] => 09214560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-15 [patent_title] => 'VTFT including overlapping electrodes' [patent_app_type] => utility [patent_app_number] => 14/198643 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 65 [patent_no_of_words] => 16717 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198643 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198643
VTFT including overlapping electrodes Mar 5, 2014 Issued
Array ( [id] => 11201030 [patent_doc_number] => 09431250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Deep well implant using blocking mask' [patent_app_type] => utility [patent_app_number] => 14/199282 [patent_app_country] => US [patent_app_date] => 2014-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3776 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14199282 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/199282
Deep well implant using blocking mask Mar 5, 2014 Issued
Array ( [id] => 10370289 [patent_doc_number] => 20150255294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'LOWERING PARASITIC CAPACITANCE OF REPLACEMENT METAL GATE PROCESSES' [patent_app_type] => utility [patent_app_number] => 14/197959 [patent_app_country] => US [patent_app_date] => 2014-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14197959 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/197959
Lowering parasitic capacitance of replacement metal gate processes Mar 4, 2014 Issued
Array ( [id] => 10370294 [patent_doc_number] => 20150255300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'DENSELY SPACED FINS FOR SEMICONDUCTOR FIN FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/198005 [patent_app_country] => US [patent_app_date] => 2014-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3057 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14198005 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/198005
Densely spaced fins for semiconductor fin field effect transistors Mar 4, 2014 Issued
Array ( [id] => 11259557 [patent_doc_number] => 09484463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Fabrication process for mitigating external resistance of a multigate device' [patent_app_type] => utility [patent_app_number] => 14/197655 [patent_app_country] => US [patent_app_date] => 2014-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 2492 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14197655 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/197655
Fabrication process for mitigating external resistance of a multigate device Mar 4, 2014 Issued
Array ( [id] => 10372276 [patent_doc_number] => 20150257282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SUBSTRATE WITH CONDUCTIVE VIAS' [patent_app_type] => utility [patent_app_number] => 14/196481 [patent_app_country] => US [patent_app_date] => 2014-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4036 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14196481 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/196481
Substrate with conductive vias Mar 3, 2014 Issued
Menu