
Austin Murata
Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )
| Most Active Art Unit | 1712 |
| Art Unit(s) | 1712, 1792 |
| Total Applications | 853 |
| Issued Applications | 467 |
| Pending Applications | 93 |
| Abandoned Applications | 315 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5471833
[patent_doc_number] => 20090244999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'Clock control during self-test of multi port memory'
[patent_app_type] => utility
[patent_app_number] => 12/076948
[patent_app_country] => US
[patent_app_date] => 2008-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3171
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0244/20090244999.pdf
[firstpage_image] =>[orig_patent_app_number] => 12076948
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/076948 | Clock control during self-test of multi port memory | Mar 24, 2008 | Issued |
Array
(
[id] => 5535342
[patent_doc_number] => 20090235130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACTURING TEST SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/048766
[patent_app_country] => US
[patent_app_date] => 2008-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3209
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20090235130.pdf
[firstpage_image] =>[orig_patent_app_number] => 12048766
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/048766 | TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACTURING TEST SYSTEM | Mar 13, 2008 | Abandoned |
Array
(
[id] => 27445
[patent_doc_number] => 07802155
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Non-volatile memory device manufacturing process testing systems and methods thereof'
[patent_app_type] => utility
[patent_app_number] => 12/042316
[patent_app_country] => US
[patent_app_date] => 2008-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 24
[patent_no_of_words] => 8022
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 469
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/802/07802155.pdf
[firstpage_image] =>[orig_patent_app_number] => 12042316
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/042316 | Non-volatile memory device manufacturing process testing systems and methods thereof | Mar 3, 2008 | Issued |
Array
(
[id] => 5263632
[patent_doc_number] => 20090116317
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-07
[patent_title] => 'Block repair apparatus and method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/070952
[patent_app_country] => US
[patent_app_date] => 2008-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2371
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0116/20090116317.pdf
[firstpage_image] =>[orig_patent_app_number] => 12070952
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/070952 | Block repair apparatus and method thereof | Feb 21, 2008 | Abandoned |
Array
(
[id] => 4836858
[patent_doc_number] => 20080133993
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-05
[patent_title] => 'ON-CHIP HIGH-SPEED SERIAL DATA ANALYZERS, SYSTEMS, AND ASSOCIATED METHODS'
[patent_app_type] => utility
[patent_app_number] => 12/030148
[patent_app_country] => US
[patent_app_date] => 2008-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2408
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20080133993.pdf
[firstpage_image] =>[orig_patent_app_number] => 12030148
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/030148 | ON-CHIP HIGH-SPEED SERIAL DATA ANALYZERS, SYSTEMS, AND ASSOCIATED METHODS | Feb 11, 2008 | Abandoned |
Array
(
[id] => 258194
[patent_doc_number] => 07577882
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-08-18
[patent_title] => 'Semiconductor integrated circuit including memory macro'
[patent_app_type] => utility
[patent_app_number] => 11/998602
[patent_app_country] => US
[patent_app_date] => 2007-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 28043
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/577/07577882.pdf
[firstpage_image] =>[orig_patent_app_number] => 11998602
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/998602 | Semiconductor integrated circuit including memory macro | Nov 29, 2007 | Issued |
Array
(
[id] => 4508728
[patent_doc_number] => 07958433
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-06-07
[patent_title] => 'Methods and systems for storing data in memory using zoning'
[patent_app_type] => utility
[patent_app_number] => 11/947581
[patent_app_country] => US
[patent_app_date] => 2007-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2619
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/958/07958433.pdf
[firstpage_image] =>[orig_patent_app_number] => 11947581
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/947581 | Methods and systems for storing data in memory using zoning | Nov 28, 2007 | Issued |
Array
(
[id] => 8308725
[patent_doc_number] => 08230278
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-24
[patent_title] => 'Test system having a sub-system to sub-system bridge'
[patent_app_type] => utility
[patent_app_number] => 11/944855
[patent_app_country] => US
[patent_app_date] => 2007-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4723
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11944855
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/944855 | Test system having a sub-system to sub-system bridge | Nov 25, 2007 | Issued |
Array
(
[id] => 5286628
[patent_doc_number] => 20090100303
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-16
[patent_title] => 'Adjustable test pattern results latency'
[patent_app_type] => utility
[patent_app_number] => 11/986508
[patent_app_country] => US
[patent_app_date] => 2007-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4198
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20090100303.pdf
[firstpage_image] =>[orig_patent_app_number] => 11986508
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/986508 | Adjustable test pattern results latency | Nov 20, 2007 | Issued |
Array
(
[id] => 4479520
[patent_doc_number] => 07945827
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-05-17
[patent_title] => 'Method and device for scan chain management of dies reused in a multi-chip package'
[patent_app_type] => utility
[patent_app_number] => 11/986529
[patent_app_country] => US
[patent_app_date] => 2007-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 11455
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 370
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/945/07945827.pdf
[firstpage_image] =>[orig_patent_app_number] => 11986529
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/986529 | Method and device for scan chain management of dies reused in a multi-chip package | Nov 19, 2007 | Issued |
Array
(
[id] => 5280744
[patent_doc_number] => 20090132876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-21
[patent_title] => 'Maintaining Error Statistics Concurrently Across Multiple Memory Ranks'
[patent_app_type] => utility
[patent_app_number] => 11/942116
[patent_app_country] => US
[patent_app_date] => 2007-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4158
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0132/20090132876.pdf
[firstpage_image] =>[orig_patent_app_number] => 11942116
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/942116 | Maintaining Error Statistics Concurrently Across Multiple Memory Ranks | Nov 18, 2007 | Abandoned |
Array
(
[id] => 4784127
[patent_doc_number] => 20080137456
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-12
[patent_title] => 'METHOD OF TESTING MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/940678
[patent_app_country] => US
[patent_app_date] => 2007-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10545
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20080137456.pdf
[firstpage_image] =>[orig_patent_app_number] => 11940678
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/940678 | METHOD OF TESTING MEMORY DEVICE | Nov 14, 2007 | Abandoned |
Array
(
[id] => 4577522
[patent_doc_number] => 07848193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-12-07
[patent_title] => 'Disc device'
[patent_app_type] => utility
[patent_app_number] => 11/977816
[patent_app_country] => US
[patent_app_date] => 2007-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 9752
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/848/07848193.pdf
[firstpage_image] =>[orig_patent_app_number] => 11977816
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/977816 | Disc device | Oct 25, 2007 | Issued |
Array
(
[id] => 4602920
[patent_doc_number] => 07979765
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-12
[patent_title] => 'Generating device, generating method, program and recording medium'
[patent_app_type] => utility
[patent_app_number] => 12/442996
[patent_app_country] => US
[patent_app_date] => 2007-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8498
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/979/07979765.pdf
[firstpage_image] =>[orig_patent_app_number] => 12442996
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/442996 | Generating device, generating method, program and recording medium | Sep 24, 2007 | Issued |
Array
(
[id] => 5448128
[patent_doc_number] => 20090049354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'Single-pass, concurrent-validation methods for generating test patterns for sequential circuits'
[patent_app_type] => utility
[patent_app_number] => 11/893683
[patent_app_country] => US
[patent_app_date] => 2007-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 14590
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20090049354.pdf
[firstpage_image] =>[orig_patent_app_number] => 11893683
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/893683 | Single-pass, concurrent-validation methods for generating test patterns for sequential circuits | Aug 15, 2007 | Issued |
Array
(
[id] => 5362989
[patent_doc_number] => 20090037783
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-05
[patent_title] => 'PROTECTING DATA STORAGE STRUCTURES FROM INTERMITTENT ERRORS'
[patent_app_type] => utility
[patent_app_number] => 11/833765
[patent_app_country] => US
[patent_app_date] => 2007-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3232
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20090037783.pdf
[firstpage_image] =>[orig_patent_app_number] => 11833765
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/833765 | Protecting data storage structures from intermittent errors | Aug 2, 2007 | Issued |
Array
(
[id] => 4798988
[patent_doc_number] => 20080010574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING AN INTEGRATED CIRCUIT ARRANGEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/763140
[patent_app_country] => US
[patent_app_date] => 2007-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2716
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20080010574.pdf
[firstpage_image] =>[orig_patent_app_number] => 11763140
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/763140 | INTEGRATED CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING AN INTEGRATED CIRCUIT ARRANGEMENT | Jun 13, 2007 | Abandoned |
Array
(
[id] => 4934056
[patent_doc_number] => 20080004831
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'Circuitry and Method for an At-Speed Scan Test'
[patent_app_type] => utility
[patent_app_number] => 11/762353
[patent_app_country] => US
[patent_app_date] => 2007-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6335
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0004/20080004831.pdf
[firstpage_image] =>[orig_patent_app_number] => 11762353
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/762353 | Circuitry and method for an at-speed scan test | Jun 12, 2007 | Issued |
Array
(
[id] => 7530042
[patent_doc_number] => 08046648
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-10-25
[patent_title] => 'Method and apparatus for controlling operating modes of an electronic device'
[patent_app_type] => utility
[patent_app_number] => 11/761815
[patent_app_country] => US
[patent_app_date] => 2007-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 11739
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/046/08046648.pdf
[firstpage_image] =>[orig_patent_app_number] => 11761815
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/761815 | Method and apparatus for controlling operating modes of an electronic device | Jun 11, 2007 | Issued |
Array
(
[id] => 5009536
[patent_doc_number] => 20070280014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/806122
[patent_app_country] => US
[patent_app_date] => 2007-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1897
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0280/20070280014.pdf
[firstpage_image] =>[orig_patent_app_number] => 11806122
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/806122 | Semiconductor device | May 29, 2007 | Abandoned |