
Austin Murata
Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )
| Most Active Art Unit | 1712 |
| Art Unit(s) | 1712, 1792 |
| Total Applications | 853 |
| Issued Applications | 467 |
| Pending Applications | 93 |
| Abandoned Applications | 315 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5064928
[patent_doc_number] => 20070226570
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-27
[patent_title] => 'SPEEDING UP DEFECT DIAGNOSIS TECHNIQUES'
[patent_app_type] => utility
[patent_app_number] => 11/688782
[patent_app_country] => US
[patent_app_date] => 2007-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 16200
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0226/20070226570.pdf
[firstpage_image] =>[orig_patent_app_number] => 11688782
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/688782 | Speeding up defect diagnosis techniques | Mar 19, 2007 | Issued |
Array
(
[id] => 4738886
[patent_doc_number] => 20080232538
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'TEST APPARATUS AND ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 11/688834
[patent_app_country] => US
[patent_app_date] => 2007-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5025
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20080232538.pdf
[firstpage_image] =>[orig_patent_app_number] => 11688834
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/688834 | TEST APPARATUS AND ELECTRONIC DEVICE | Mar 19, 2007 | Abandoned |
Array
(
[id] => 5565917
[patent_doc_number] => 20090138770
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-28
[patent_title] => 'TEST SYSTEM OF RECONFIGURABLE DEVICE AND ITS METHOD AND RECONFIGURABLE DEVICE FOR USE THEREIN'
[patent_app_type] => utility
[patent_app_number] => 12/282482
[patent_app_country] => US
[patent_app_date] => 2007-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 8515
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20090138770.pdf
[firstpage_image] =>[orig_patent_app_number] => 12282482
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/282482 | Test system of reconfigurable device and its method and reconfigurable device for use therein | Feb 28, 2007 | Issued |
Array
(
[id] => 4754937
[patent_doc_number] => 20080163013
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-07-03
[patent_title] => 'Memory testing system and method'
[patent_app_type] => utility
[patent_app_number] => 11/648142
[patent_app_country] => US
[patent_app_date] => 2006-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3201
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20080163013.pdf
[firstpage_image] =>[orig_patent_app_number] => 11648142
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/648142 | Memory testing system and method | Dec 28, 2006 | Abandoned |
Array
(
[id] => 5235144
[patent_doc_number] => 20070127300
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-07
[patent_title] => 'Bun-in test method semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/647398
[patent_app_country] => US
[patent_app_date] => 2006-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8054
[patent_no_of_claims] => 10
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[pdf_file] => publications/A1/0127/20070127300.pdf
[firstpage_image] =>[orig_patent_app_number] => 11647398
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/647398 | Bun-in test method semiconductor memory device | Dec 28, 2006 | Abandoned |
Array
(
[id] => 166789
[patent_doc_number] => 07673203
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-03-02
[patent_title] => 'Interconnect delay fault test controller and test apparatus using the same'
[patent_app_type] => utility
[patent_app_number] => 11/616471
[patent_app_country] => US
[patent_app_date] => 2006-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3969
[patent_no_of_claims] => 12
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/673/07673203.pdf
[firstpage_image] =>[orig_patent_app_number] => 11616471
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/616471 | Interconnect delay fault test controller and test apparatus using the same | Dec 26, 2006 | Issued |
Array
(
[id] => 4865353
[patent_doc_number] => 20080144412
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-19
[patent_title] => 'METHOD AND DEVICE FOR TESTING MEMORY'
[patent_app_type] => utility
[patent_app_number] => 11/611715
[patent_app_country] => US
[patent_app_date] => 2006-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5081
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0144/20080144412.pdf
[firstpage_image] =>[orig_patent_app_number] => 11611715
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/611715 | Method and device for testing memory | Dec 14, 2006 | Issued |
Array
(
[id] => 5081411
[patent_doc_number] => 20070124635
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-31
[patent_title] => 'INTEGRATION CIRCUIT AND TEST METHOD OF THE SAME'
[patent_app_type] => utility
[patent_app_number] => 11/555389
[patent_app_country] => US
[patent_app_date] => 2006-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3985
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20070124635.pdf
[firstpage_image] =>[orig_patent_app_number] => 11555389
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/555389 | INTEGRATION CIRCUIT AND TEST METHOD OF THE SAME | Oct 31, 2006 | Abandoned |
Array
(
[id] => 4905612
[patent_doc_number] => 20080115026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-15
[patent_title] => 'Method and Apparatus for Scheduling BIST Routines'
[patent_app_type] => utility
[patent_app_number] => 11/553609
[patent_app_country] => US
[patent_app_date] => 2006-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4496
[patent_no_of_claims] => 32
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20080115026.pdf
[firstpage_image] =>[orig_patent_app_number] => 11553609
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/553609 | Method and apparatus for scheduling BIST routines | Oct 26, 2006 | Issued |
Array
(
[id] => 4905611
[patent_doc_number] => 20080115025
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-15
[patent_title] => 'Circuit and method operable in functional and diagnostic modes'
[patent_app_type] => utility
[patent_app_number] => 11/582517
[patent_app_country] => US
[patent_app_date] => 2006-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 5141
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0115/20080115025.pdf
[firstpage_image] =>[orig_patent_app_number] => 11582517
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/582517 | Circuit and method operable in functional and diagnostic modes | Oct 17, 2006 | Issued |
Array
(
[id] => 4973130
[patent_doc_number] => 20070113133
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-17
[patent_title] => 'SYSTEM AND METHOD FOR TESTING A SERIAL PORT'
[patent_app_type] => utility
[patent_app_number] => 11/309790
[patent_app_country] => US
[patent_app_date] => 2006-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3222
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20070113133.pdf
[firstpage_image] =>[orig_patent_app_number] => 11309790
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/309790 | SYSTEM AND METHOD FOR TESTING A SERIAL PORT | Sep 26, 2006 | Abandoned |
Array
(
[id] => 4945553
[patent_doc_number] => 20080082880
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'METHOD OF TESTING HIGH-SPEED IC WITH LOW-SPEED IC TESTER'
[patent_app_type] => utility
[patent_app_number] => 11/470312
[patent_app_country] => US
[patent_app_date] => 2006-09-06
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[pdf_file] => publications/A1/0082/20080082880.pdf
[firstpage_image] =>[orig_patent_app_number] => 11470312
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/470312 | METHOD OF TESTING HIGH-SPEED IC WITH LOW-SPEED IC TESTER | Sep 5, 2006 | Abandoned |
Array
(
[id] => 4945561
[patent_doc_number] => 20080082888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'Measurement and calibration method for embedded diagnostic systems'
[patent_app_type] => utility
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11515056
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/515056 | Measurement and calibration method for embedded diagnostic systems | Aug 31, 2006 | Abandoned |
Array
(
[id] => 4923802
[patent_doc_number] => 20080072119
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'Allowable bit errors per sector in memory devices'
[patent_app_type] => utility
[patent_app_number] => 11/515048
[patent_app_country] => US
[patent_app_date] => 2006-08-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0072/20080072119.pdf
[firstpage_image] =>[orig_patent_app_number] => 11515048
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/515048 | Allowable bit errors per sector in memory devices | Aug 30, 2006 | Abandoned |
Array
(
[id] => 5047463
[patent_doc_number] => 20070266137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-11-15
[patent_title] => 'Method and apparatus for automated testing of multiple device platforms through a command line interface'
[patent_app_type] => utility
[patent_app_number] => 11/515115
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[firstpage_image] =>[orig_patent_app_number] => 11515115
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/515115 | Method and apparatus for automated testing of multiple device platforms through a command line interface | Aug 30, 2006 | Abandoned |
Array
(
[id] => 4923801
[patent_doc_number] => 20080072118
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-03-20
[patent_title] => 'Yield-Enhancing Device Failure Analysis'
[patent_app_type] => utility
[patent_app_number] => 11/468838
[patent_app_country] => US
[patent_app_date] => 2006-08-31
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[pdf_file] => publications/A1/0072/20080072118.pdf
[firstpage_image] =>[orig_patent_app_number] => 11468838
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/468838 | Yield-enhancing device failure analysis | Aug 30, 2006 | Issued |
Array
(
[id] => 5058717
[patent_doc_number] => 20070061639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-15
[patent_title] => 'Semiconductor device test system with test interface means'
[patent_app_type] => utility
[patent_app_number] => 11/513964
[patent_app_country] => US
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[pdf_file] => publications/A1/0061/20070061639.pdf
[firstpage_image] =>[orig_patent_app_number] => 11513964
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/513964 | Semiconductor device test system with test interface means | Aug 30, 2006 | Issued |
Array
(
[id] => 321470
[patent_doc_number] => 07523373
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[patent_kind] => B2
[patent_issue_date] => 2009-04-21
[patent_title] => 'Minimum memory operating voltage technique'
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[patent_app_number] => 11/468458
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[firstpage_image] =>[orig_patent_app_number] => 11468458
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/468458 | Minimum memory operating voltage technique | Aug 29, 2006 | Issued |
Array
(
[id] => 4945559
[patent_doc_number] => 20080082886
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'Sub-instruction repeats for algorithmic pattern generators'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/513087 | Sub-instruction repeats for algorithmic pattern generators | Aug 29, 2006 | Issued |
Array
(
[id] => 5058699
[patent_doc_number] => 20070061621
[patent_country] => US
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[patent_issue_date] => 2007-03-15
[patent_title] => 'Fault diagnosis apparatus and method for system-on-chip (SoC) and SoC in which fault is capable of being diagnosed'
[patent_app_type] => utility
[patent_app_number] => 11/512375
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[pdf_file] => publications/A1/0061/20070061621.pdf
[firstpage_image] =>[orig_patent_app_number] => 11512375
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/512375 | Fault diagnosis apparatus and method for system-on-chip (SoC) and SoC in which fault is capable of being diagnosed | Aug 29, 2006 | Abandoned |