Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4671728 [patent_doc_number] => 20080046789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/465864 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20080046789.pdf [firstpage_image] =>[orig_patent_app_number] => 11465864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465864
APPARATUS AND METHOD FOR TESTING MEMORY DEVICES AND CIRCUITS IN INTEGRATED CIRCUITS Aug 20, 2006 Abandoned
Array ( [id] => 5058728 [patent_doc_number] => 20070061650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'SEMICONDUCTOR DEVICE WITH TEST INTERFACE' [patent_app_type] => utility [patent_app_number] => 11/465540 [patent_app_country] => US [patent_app_date] => 2006-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3108 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061650.pdf [firstpage_image] =>[orig_patent_app_number] => 11465540 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465540
Semiconductor device with test interface Aug 17, 2006 Issued
Array ( [id] => 4984454 [patent_doc_number] => 20070089013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'SYSTEM AND METHOD FOR TESTING PORTS OF A COMPUTER' [patent_app_type] => utility [patent_app_number] => 11/309339 [patent_app_country] => US [patent_app_date] => 2006-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2256 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20070089013.pdf [firstpage_image] =>[orig_patent_app_number] => 11309339 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309339
SYSTEM AND METHOD FOR TESTING PORTS OF A COMPUTER Jul 27, 2006 Abandoned
Array ( [id] => 5050270 [patent_doc_number] => 20070030814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Memory module and method thereof' [patent_app_type] => utility [patent_app_number] => 11/489446 [patent_app_country] => US [patent_app_date] => 2006-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6784 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20070030814.pdf [firstpage_image] =>[orig_patent_app_number] => 11489446 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/489446
Memory module and method thereof Jul 19, 2006 Abandoned
Array ( [id] => 37682 [patent_doc_number] => 07793178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Cell supporting scan-based tests and with reduced time delay in functional mode' [patent_app_type] => utility [patent_app_number] => 11/309191 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 5024 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/793/07793178.pdf [firstpage_image] =>[orig_patent_app_number] => 11309191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309191
Cell supporting scan-based tests and with reduced time delay in functional mode Jul 11, 2006 Issued
Array ( [id] => 27454 [patent_doc_number] => 07802157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Test mode for multi-chip integrated circuit packages' [patent_app_type] => utility [patent_app_number] => 11/472618 [patent_app_country] => US [patent_app_date] => 2006-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4564 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802157.pdf [firstpage_image] =>[orig_patent_app_number] => 11472618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/472618
Test mode for multi-chip integrated circuit packages Jun 21, 2006 Issued
Array ( [id] => 5200800 [patent_doc_number] => 20070300118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'Method and system for controlling multiple physical pin electronics channels in a semiconductor test head' [patent_app_type] => utility [patent_app_number] => 11/448385 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3464 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0300/20070300118.pdf [firstpage_image] =>[orig_patent_app_number] => 11448385 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/448385
Method and system for controlling multiple physical pin electronics channels in a semiconductor test head Jun 5, 2006 Abandoned
Array ( [id] => 7530049 [patent_doc_number] => 08046655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Area efficient memory architecture with decoder self test and debug capability' [patent_app_type] => utility [patent_app_number] => 11/437420 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4233 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/046/08046655.pdf [firstpage_image] =>[orig_patent_app_number] => 11437420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/437420
Area efficient memory architecture with decoder self test and debug capability May 17, 2006 Issued
Array ( [id] => 5852991 [patent_doc_number] => 20060236182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Scan-based self-test structure and method using weighted scan-enable signals' [patent_app_type] => utility [patent_app_number] => 11/368015 [patent_app_country] => US [patent_app_date] => 2006-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6868 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236182.pdf [firstpage_image] =>[orig_patent_app_number] => 11368015 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/368015
Scan-based self-test structure and method using weighted scan-enable signals Mar 2, 2006 Issued
Array ( [id] => 5190505 [patent_doc_number] => 20070168814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Device and method for testing and for diagnosing digital circuits' [patent_app_type] => utility [patent_app_number] => 11/364369 [patent_app_country] => US [patent_app_date] => 2006-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11953 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168814.pdf [firstpage_image] =>[orig_patent_app_number] => 11364369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/364369
Device and method for testing and for diagnosing digital circuits Feb 28, 2006 Issued
Array ( [id] => 5132571 [patent_doc_number] => 20070208968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-06 [patent_title] => 'At-speed multi-port memory array test method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/365648 [patent_app_country] => US [patent_app_date] => 2006-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3837 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20070208968.pdf [firstpage_image] =>[orig_patent_app_number] => 11365648 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/365648
At-speed multi-port memory array test method and apparatus Feb 28, 2006 Abandoned
Array ( [id] => 5674019 [patent_doc_number] => 20060179374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Wireless hardware debugging' [patent_app_type] => utility [patent_app_number] => 11/348745 [patent_app_country] => US [patent_app_date] => 2006-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3982 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20060179374.pdf [firstpage_image] =>[orig_patent_app_number] => 11348745 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348745
Wireless hardware debugging Feb 6, 2006 Abandoned
Array ( [id] => 5102420 [patent_doc_number] => 20070185682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Time-aware trigger distribution' [patent_app_type] => utility [patent_app_number] => 11/348741 [patent_app_country] => US [patent_app_date] => 2006-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4455 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20070185682.pdf [firstpage_image] =>[orig_patent_app_number] => 11348741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/348741
Time-aware trigger distribution Feb 5, 2006 Abandoned
Array ( [id] => 8878812 [patent_doc_number] => 08473796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Error detection in compressed data' [patent_app_type] => utility [patent_app_number] => 11/342177 [patent_app_country] => US [patent_app_date] => 2006-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4094 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11342177 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/342177
Error detection in compressed data Jan 26, 2006 Issued
Array ( [id] => 4479530 [patent_doc_number] => 07945829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/795842 [patent_app_country] => US [patent_app_date] => 2006-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 21038 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/945/07945829.pdf [firstpage_image] =>[orig_patent_app_number] => 11795842 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/795842
Semiconductor integrated circuit Jan 4, 2006 Issued
Array ( [id] => 5215031 [patent_doc_number] => 20070104111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Internal analog loopback for a high-speed interface test' [patent_app_type] => utility [patent_app_number] => 11/267436 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20070104111.pdf [firstpage_image] =>[orig_patent_app_number] => 11267436 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/267436
Internal analog loopback for a high-speed interface test Nov 3, 2005 Abandoned
Array ( [id] => 5746863 [patent_doc_number] => 20060109794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Communication system' [patent_app_type] => utility [patent_app_number] => 11/261622 [patent_app_country] => US [patent_app_date] => 2005-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20060109794.pdf [firstpage_image] =>[orig_patent_app_number] => 11261622 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261622
Communication system Oct 30, 2005 Abandoned
Array ( [id] => 5809461 [patent_doc_number] => 20060095817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Buffer for testing a memory module and method thereof' [patent_app_type] => utility [patent_app_number] => 11/260318 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6190 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095817.pdf [firstpage_image] =>[orig_patent_app_number] => 11260318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/260318
Buffer for testing a memory module and method thereof Oct 27, 2005 Abandoned
Array ( [id] => 5036675 [patent_doc_number] => 20070101214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Self-testing apparatus with controllable environmental stress screening (ESS)' [patent_app_type] => utility [patent_app_number] => 11/261038 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7029 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101214.pdf [firstpage_image] =>[orig_patent_app_number] => 11261038 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261038
Self-testing apparatus with controllable environmental stress screening (ESS) Oct 27, 2005 Abandoned
Array ( [id] => 598951 [patent_doc_number] => 07447962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'JTAG interface using existing I/O bus' [patent_app_type] => utility [patent_app_number] => 11/255150 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 14173 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/447/07447962.pdf [firstpage_image] =>[orig_patent_app_number] => 11255150 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/255150
JTAG interface using existing I/O bus Oct 20, 2005 Issued
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