Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 66576 [patent_doc_number] => 07765450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Methods for distribution of test generation programs' [patent_app_type] => utility [patent_app_number] => 11/256211 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 13997 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/765/07765450.pdf [firstpage_image] =>[orig_patent_app_number] => 11256211 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256211
Methods for distribution of test generation programs Oct 19, 2005 Issued
Array ( [id] => 5042272 [patent_doc_number] => 20070094554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Chip specific test mode execution on a memory module' [patent_app_type] => utility [patent_app_number] => 11/253716 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094554.pdf [firstpage_image] =>[orig_patent_app_number] => 11253716 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/253716
Chip specific test mode execution on a memory module Oct 19, 2005 Abandoned
Array ( [id] => 4984434 [patent_doc_number] => 20070088993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Memory tester having master/slave configuration' [patent_app_type] => utility [patent_app_number] => 11/252435 [patent_app_country] => US [patent_app_date] => 2005-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3302 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20070088993.pdf [firstpage_image] =>[orig_patent_app_number] => 11252435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/252435
Memory tester having master/slave configuration Oct 17, 2005 Abandoned
Array ( [id] => 5195315 [patent_doc_number] => 20070083800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'System and method for varying test signal durations and assert times for testing memory devices' [patent_app_type] => utility [patent_app_number] => 11/248724 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5525 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083800.pdf [firstpage_image] =>[orig_patent_app_number] => 11248724 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/248724
System and method for varying test signal durations and assert times for testing memory devices Oct 10, 2005 Issued
Array ( [id] => 5816624 [patent_doc_number] => 20060085715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Test board of semiconductor tester having modified input/output printed circuit pattern and testing method using the same' [patent_app_type] => utility [patent_app_number] => 11/243053 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3624 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20060085715.pdf [firstpage_image] =>[orig_patent_app_number] => 11243053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/243053
Test board of semiconductor tester having modified input/output printed circuit pattern and testing method using the same Oct 2, 2005 Abandoned
Array ( [id] => 5190500 [patent_doc_number] => 20070168809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Systems and methods for LBIST testing using commonly controlled LBIST satellites' [patent_app_type] => utility [patent_app_number] => 11/199972 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168809.pdf [firstpage_image] =>[orig_patent_app_number] => 11199972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199972
Systems and methods for LBIST testing using commonly controlled LBIST satellites Aug 8, 2005 Abandoned
Array ( [id] => 5273662 [patent_doc_number] => 20090077438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'CIRCUIT INTERCONNECT TESTING ARRANGEMENT AND APPROACH THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/572808 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4966 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077438.pdf [firstpage_image] =>[orig_patent_app_number] => 11572808 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/572808
Circuit interconnect testing arrangement and approach therefor Jul 27, 2005 Issued
Array ( [id] => 5243849 [patent_doc_number] => 20070022344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Digital storage element architecture comprising dual scan clocks and gated scan output' [patent_app_type] => utility [patent_app_number] => 11/171537 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11681 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20070022344.pdf [firstpage_image] =>[orig_patent_app_number] => 11171537 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171537
Digital storage element architecture comprising dual scan clocks and gated scan output Jun 29, 2005 Issued
Array ( [id] => 5243842 [patent_doc_number] => 20070022337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Method and apparatus to verify non-deterministic results in an efficient random manner' [patent_app_type] => utility [patent_app_number] => 11/171783 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3084 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20070022337.pdf [firstpage_image] =>[orig_patent_app_number] => 11171783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171783
Method and apparatus to verify non-deterministic results in an efficient random manner Jun 29, 2005 Issued
Array ( [id] => 605114 [patent_doc_number] => 07434152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Multiple-level data compression read mode for memory testing' [patent_app_type] => utility [patent_app_number] => 11/127810 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8280 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/434/07434152.pdf [firstpage_image] =>[orig_patent_app_number] => 11127810 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/127810
Multiple-level data compression read mode for memory testing May 11, 2005 Issued
Array ( [id] => 305834 [patent_doc_number] => 07536617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Programmable in-situ delay fault test clock generator' [patent_app_type] => utility [patent_app_number] => 11/103877 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4813 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536617.pdf [firstpage_image] =>[orig_patent_app_number] => 11103877 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/103877
Programmable in-situ delay fault test clock generator Apr 11, 2005 Issued
Array ( [id] => 5696045 [patent_doc_number] => 20060156192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/102715 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5524 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156192.pdf [firstpage_image] =>[orig_patent_app_number] => 11102715 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/102715
Semiconductor memory device Apr 10, 2005 Issued
Array ( [id] => 5812211 [patent_doc_number] => 20060083084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Semiconductor test system' [patent_app_type] => utility [patent_app_number] => 11/081684 [patent_app_country] => US [patent_app_date] => 2005-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7414 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083084.pdf [firstpage_image] =>[orig_patent_app_number] => 11081684 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/081684
Semiconductor test system Mar 16, 2005 Issued
Array ( [id] => 5684442 [patent_doc_number] => 20060200712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'System and method for testing memory' [patent_app_type] => utility [patent_app_number] => 11/070970 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5685 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20060200712.pdf [firstpage_image] =>[orig_patent_app_number] => 11070970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/070970
System and method for testing memory Mar 2, 2005 Issued
Array ( [id] => 846278 [patent_doc_number] => 07389449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Edge selecting triggering circuit' [patent_app_type] => utility [patent_app_number] => 11/069879 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4839 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/389/07389449.pdf [firstpage_image] =>[orig_patent_app_number] => 11069879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/069879
Edge selecting triggering circuit Feb 27, 2005 Issued
Array ( [id] => 7178215 [patent_doc_number] => 20050204233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-15 [patent_title] => 'System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC' [patent_app_type] => utility [patent_app_number] => 11/066585 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7987 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20050204233.pdf [firstpage_image] =>[orig_patent_app_number] => 11066585 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066585
System-on-chip (SOC) having built-in-self-test circuits and a self-test method of the SOC Feb 24, 2005 Issued
Array ( [id] => 374996 [patent_doc_number] => 07475304 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-06 [patent_title] => 'Bit error tester' [patent_app_type] => utility [patent_app_number] => 11/070576 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2568 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/475/07475304.pdf [firstpage_image] =>[orig_patent_app_number] => 11070576 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/070576
Bit error tester Feb 24, 2005 Issued
Array ( [id] => 596903 [patent_doc_number] => 07454681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Automatic test system with synchronized instruments' [patent_app_type] => utility [patent_app_number] => 11/063289 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10771 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454681.pdf [firstpage_image] =>[orig_patent_app_number] => 11063289 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/063289
Automatic test system with synchronized instruments Feb 21, 2005 Issued
Array ( [id] => 5695970 [patent_doc_number] => 20060156117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Processor, its error analytical method and program' [patent_app_type] => utility [patent_app_number] => 11/056357 [patent_app_country] => US [patent_app_date] => 2005-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7624 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156117.pdf [firstpage_image] =>[orig_patent_app_number] => 11056357 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/056357
Processor, its error analytical method and program Feb 13, 2005 Abandoned
Array ( [id] => 5879253 [patent_doc_number] => 20060168490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Apparatus and method of controlling test modes of a scannable latch in a test scan chain' [patent_app_type] => utility [patent_app_number] => 11/041584 [patent_app_country] => US [patent_app_date] => 2005-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5378 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20060168490.pdf [firstpage_image] =>[orig_patent_app_number] => 11041584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/041584
Apparatus and method of controlling test modes of a scannable latch in a test scan chain Jan 23, 2005 Abandoned
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