Austin Murata

Array ( [id] => 6995389 [patent_doc_number] => 20050135167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Memory access circuit for adjusting delay of internal clock signal used for memory control' [patent_app_type] => utility [patent_app_number] => 10/950471 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12990 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20050135167.pdf [firstpage_image] =>[orig_patent_app_number] => 10950471 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5638998 [patent_doc_number] => 20060069972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-30 [patent_title] => 'Methods and computer program products for debugging clock-related scan testing failures of integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/950637 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4899 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20060069972.pdf [firstpage_image] =>[orig_patent_app_number] => 10950637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6907199 [patent_doc_number] => 20050102594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Method for test application and test content generation for AC faults in integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/951278 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8418 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20050102594.pdf [firstpage_image] =>[orig_patent_app_number] => 10951278 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6992524 [patent_doc_number] => 20050091561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Scan test method, device, and system' [patent_app_type] => utility [patent_app_number] => 10/947209 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6206 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20050091561.pdf [firstpage_image] =>[orig_patent_app_number] => 10947209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7260499 [patent_doc_number] => 20050076277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Test apparatus with static storage device and test method' [patent_app_type] => utility [patent_app_number] => 10/947564 [patent_app_country] => US [patent_app_date] => 2004-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3747 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20050076277.pdf [firstpage_image] =>[orig_patent_app_number] => 10947564 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6992526 [patent_doc_number] => 20050091563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'On chip diagnosis block with mixed redundancy' [patent_app_type] => utility [patent_app_number] => 10/942274 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 2548 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20050091563.pdf [firstpage_image] =>[orig_patent_app_number] => 10942274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7129363 [patent_doc_number] => 20050060621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Method and system for direct access memory testing of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/940146 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5782 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20050060621.pdf [firstpage_image] =>[orig_patent_app_number] => 10940146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6927581 [patent_doc_number] => 20050240838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Semiconductor memory device having code bit cell array' [patent_app_type] => utility [patent_app_number] => 10/928168 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5724 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240838.pdf [firstpage_image] =>[orig_patent_app_number] => 10928168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7223289 [patent_doc_number] => 20050055618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Test arrangement and method for selecting a test mode output channel' [patent_app_type] => utility [patent_app_number] => 10/926371 [patent_app_country] => US [patent_app_date] => 2004-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4239 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055618.pdf [firstpage_image] =>[orig_patent_app_number] => 10926371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7441023 [patent_doc_number] => 20040163022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Low overhead input and output boundary scan cells' [patent_app_type] => new [patent_app_number] => 10/773784 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10198 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20040163022.pdf [firstpage_image] =>[orig_patent_app_number] => 10773784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7418868 [patent_doc_number] => 20040177300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Apparatus with a test interface' [patent_app_type] => new [patent_app_number] => 10/482015 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5054 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177300.pdf [firstpage_image] =>[orig_patent_app_number] => 10482015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7418912 [patent_doc_number] => 20040177306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Transmission device and transmission method' [patent_app_type] => new [patent_app_number] => 10/480822 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5417 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177306.pdf [firstpage_image] =>[orig_patent_app_number] => 10480822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7284638 [patent_doc_number] => 20040145939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Non-volatile semiconductor storage device and production method thereof' [patent_app_type] => new [patent_app_number] => 10/478095 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10488 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20040145939.pdf [firstpage_image] =>[orig_patent_app_number] => 10478095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7477165 [patent_doc_number] => 20040098648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Boundary scan with strobed pad driver enable' [patent_app_type] => new [patent_app_number] => 10/701479 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4263 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098648.pdf [firstpage_image] =>[orig_patent_app_number] => 10701479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 280084 [patent_doc_number] => 07559012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Method for error detection and flow direction determination in a measuring meter' [patent_app_type] => utility [patent_app_number] => 10/701027 [patent_app_country] => US [patent_app_date] => 2003-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 4920 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/559/07559012.pdf [firstpage_image] =>[orig_patent_app_number] => 10701027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6920116 [patent_doc_number] => 20050097417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Novel bisr mode to test the redundant elements and regular functional memory to avoid test escapes' [patent_app_type] => utility [patent_app_number] => 10/701332 [patent_app_country] => US [patent_app_date] => 2003-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1351 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097417.pdf [firstpage_image] =>[orig_patent_app_number] => 10701332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7341654 [patent_doc_number] => 20040133825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Path delay measuring circuitry' [patent_app_type] => new [patent_app_number] => 10/698532 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2767 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20040133825.pdf [firstpage_image] =>[orig_patent_app_number] => 10698532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6920115 [patent_doc_number] => 20050097416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Testing of integrated circuits using boundary scan' [patent_app_type] => utility [patent_app_number] => 10/699606 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5927 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097416.pdf [firstpage_image] =>[orig_patent_app_number] => 10699606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 157933 [patent_doc_number] => 07685485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'Functional failure analysis techniques for programmable integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/698739 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3629 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/685/07685485.pdf [firstpage_image] =>[orig_patent_app_number] => 10698739 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7320777 [patent_doc_number] => 20040136376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Processing of segmented messages' [patent_app_type] => new [patent_app_number] => 10/476216 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1141 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20040136376.pdf [firstpage_image] =>[orig_patent_app_number] => 10476216 [rel_patent_id] =>[rel_patent_doc_number] =>)