
Austin Murata
Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )
| Most Active Art Unit | 1712 |
| Art Unit(s) | 1712, 1792 |
| Total Applications | 853 |
| Issued Applications | 467 |
| Pending Applications | 93 |
| Abandoned Applications | 315 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7215782
[patent_doc_number] => 20040088634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Apparatus for controlling hybrid automatic repeat request (HARQ) in a mobile communication system'
[patent_app_type] => new
[patent_app_number] => 10/691644
[patent_app_country] => US
[patent_app_date] => 2003-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 15683
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0088/20040088634.pdf
[firstpage_image] =>[orig_patent_app_number] => 10691644
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/691644 | Apparatus for controlling hybrid automatic repeat request (HARQ) in a mobile communication system | Oct 23, 2003 | Issued |
Array
(
[id] => 7341691
[patent_doc_number] => 20040133834
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Lsi inspection method and apparatus, and ls1 tester'
[patent_app_type] => new
[patent_app_number] => 10/475327
[patent_app_country] => US
[patent_app_date] => 2003-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8223
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20040133834.pdf
[firstpage_image] =>[orig_patent_app_number] => 10475327
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/475327 | Lsi inspection method and apparatus, and ls1 tester | Oct 20, 2003 | Abandoned |
Array
(
[id] => 816589
[patent_doc_number] => 07415640
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-08-19
[patent_title] => 'Methods and apparatuses that reduce the size of a repair data container for repairable memories'
[patent_app_type] => utility
[patent_app_number] => 10/684793
[patent_app_country] => US
[patent_app_date] => 2003-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7484
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/415/07415640.pdf
[firstpage_image] =>[orig_patent_app_number] => 10684793
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/684793 | Methods and apparatuses that reduce the size of a repair data container for repairable memories | Oct 12, 2003 | Issued |
Array
(
[id] => 7353769
[patent_doc_number] => 20040193970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Receiver system with adjustable sampling and reference levels'
[patent_app_type] => new
[patent_app_number] => 10/404783
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2409
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20040193970.pdf
[firstpage_image] =>[orig_patent_app_number] => 10404783
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/404783 | Receiver system with adjustable sampling and reference levels | Mar 30, 2003 | Abandoned |
Array
(
[id] => 7138720
[patent_doc_number] => 20040044938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-04
[patent_title] => 'System for testing different types of semiconductor devices in parallel at the same time'
[patent_app_type] => new
[patent_app_number] => 10/404984
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2416
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0044/20040044938.pdf
[firstpage_image] =>[orig_patent_app_number] => 10404984
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/404984 | System for testing different types of semiconductor devices in parallel at the same time | Mar 30, 2003 | Abandoned |
Array
(
[id] => 4559616
[patent_doc_number] => 07877652
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-01-25
[patent_title] => 'Detection circuit and method for AC coupled circuitry'
[patent_app_type] => utility
[patent_app_number] => 10/404573
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 4170
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/877/07877652.pdf
[firstpage_image] =>[orig_patent_app_number] => 10404573
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/404573 | Detection circuit and method for AC coupled circuitry | Mar 30, 2003 | Issued |
Array
(
[id] => 7521088
[patent_doc_number] => 07975197
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-05
[patent_title] => 'On-chip scan clock generator for ASIC testing'
[patent_app_type] => utility
[patent_app_number] => 10/404306
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3549
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/975/07975197.pdf
[firstpage_image] =>[orig_patent_app_number] => 10404306
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/404306 | On-chip scan clock generator for ASIC testing | Mar 30, 2003 | Issued |
Array
(
[id] => 7353879
[patent_doc_number] => 20040193986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'On-die pattern generator for high speed serial interconnect built-in self test'
[patent_app_type] => new
[patent_app_number] => 10/404622
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3203
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20040193986.pdf
[firstpage_image] =>[orig_patent_app_number] => 10404622
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/404622 | On-die pattern generator for high speed serial interconnect built-in self test | Mar 30, 2003 | Abandoned |
Array
(
[id] => 7353863
[patent_doc_number] => 20040193984
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Signature Cell'
[patent_app_type] => new
[patent_app_number] => 10/402536
[patent_app_country] => US
[patent_app_date] => 2003-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5645
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20040193984.pdf
[firstpage_image] =>[orig_patent_app_number] => 10402536
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/402536 | Signature Cell | Mar 27, 2003 | Abandoned |
Array
(
[id] => 6732046
[patent_doc_number] => 20030188236
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Method of testing memory device'
[patent_app_type] => new
[patent_app_number] => 10/402181
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 10702
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20030188236.pdf
[firstpage_image] =>[orig_patent_app_number] => 10402181
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/402181 | Method of testing memory device | Mar 26, 2003 | Issued |
Array
(
[id] => 600423
[patent_doc_number] => 07437633
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-10-14
[patent_title] => 'Duty cycle characterization and adjustment'
[patent_app_type] => utility
[patent_app_number] => 10/402837
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 27
[patent_no_of_words] => 16302
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 425
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/437/07437633.pdf
[firstpage_image] =>[orig_patent_app_number] => 10402837
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/402837 | Duty cycle characterization and adjustment | Mar 26, 2003 | Issued |
Array
(
[id] => 7353813
[patent_doc_number] => 20040193975
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-30
[patent_title] => 'Method and an apparatus for transmit phase select'
[patent_app_type] => new
[patent_app_number] => 10/400975
[patent_app_country] => US
[patent_app_date] => 2003-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_claims] => 32
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0193/20040193975.pdf
[firstpage_image] =>[orig_patent_app_number] => 10400975
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/400975 | Method and an apparatus for transmit phase select | Mar 25, 2003 | Abandoned |
Array
(
[id] => 6679703
[patent_doc_number] => 20030229844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-11
[patent_title] => 'Graceful degradation of serial channels'
[patent_app_type] => new
[patent_app_number] => 10/396287
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[pdf_file] => publications/A1/0229/20030229844.pdf
[firstpage_image] =>[orig_patent_app_number] => 10396287
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/396287 | Graceful degradation of serial channels | Mar 23, 2003 | Abandoned |
Array
(
[id] => 6826410
[patent_doc_number] => 20030237032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'Method for electronically testing memory modules'
[patent_app_type] => new
[patent_app_number] => 10/395454
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 7197
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0237/20030237032.pdf
[firstpage_image] =>[orig_patent_app_number] => 10395454
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/395454 | Method for electronically testing memory modules | Mar 23, 2003 | Abandoned |
Array
(
[id] => 7457827
[patent_doc_number] => 20040187060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Generating test patterns for testing an integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/393844
[patent_app_country] => US
[patent_app_date] => 2003-03-21
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0187/20040187060.pdf
[firstpage_image] =>[orig_patent_app_number] => 10393844
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/393844 | Generating test patterns for testing an integrated circuit | Mar 20, 2003 | Abandoned |
Array
(
[id] => 7457762
[patent_doc_number] => 20040187051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Memory error generating method, apparatus and computer program product'
[patent_app_type] => new
[patent_app_number] => 10/392759
[patent_app_country] => US
[patent_app_date] => 2003-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0187/20040187051.pdf
[firstpage_image] =>[orig_patent_app_number] => 10392759
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/392759 | Memory error generating method, apparatus and computer program product | Mar 19, 2003 | Abandoned |
Array
(
[id] => 7473000
[patent_doc_number] => 20040199838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Enhanced boundary-scan method and apparatus providing tester channel reduction'
[patent_app_type] => new
[patent_app_number] => 10/392011
[patent_app_country] => US
[patent_app_date] => 2003-03-19
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20040199838.pdf
[firstpage_image] =>[orig_patent_app_number] => 10392011
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/392011 | Enhanced boundary-scan method and apparatus providing tester channel reduction | Mar 18, 2003 | Abandoned |
Array
(
[id] => 6831549
[patent_doc_number] => 20030182607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-09-25
[patent_title] => 'Semiconductor memory device and method of testing same'
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[patent_app_number] => 10/390759
[patent_app_country] => US
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0182/20030182607.pdf
[firstpage_image] =>[orig_patent_app_number] => 10390759
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/390759 | Semiconductor memory device and method of testing same | Mar 18, 2003 | Issued |
Array
(
[id] => 7457755
[patent_doc_number] => 20040187050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-23
[patent_title] => 'Test structure and method for accurate determination of soft error of logic components'
[patent_app_type] => new
[patent_app_number] => 10/392099
[patent_app_country] => US
[patent_app_date] => 2003-03-19
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[pdf_file] => publications/A1/0187/20040187050.pdf
[firstpage_image] =>[orig_patent_app_number] => 10392099
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/392099 | Test structure and method for accurate determination of soft error of logic components | Mar 18, 2003 | Abandoned |
Array
(
[id] => 6866073
[patent_doc_number] => 20030191599
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'Method and protocol tester for decoding data encoded in accordance with a protocol description'
[patent_app_type] => new
[patent_app_number] => 10/391986
[patent_app_country] => US
[patent_app_date] => 2003-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20030191599.pdf
[firstpage_image] =>[orig_patent_app_number] => 10391986
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/391986 | Method and protocol tester for decoding data encoded in accordance with a protocol description | Mar 17, 2003 | Issued |