
Austin Murata
Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )
| Most Active Art Unit | 1712 |
| Art Unit(s) | 1712, 1792 |
| Total Applications | 853 |
| Issued Applications | 467 |
| Pending Applications | 93 |
| Abandoned Applications | 315 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6698233
[patent_doc_number] => 20030110427
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-12
[patent_title] => 'Semiconductor test system storing pin calibration data in non-volatile memory'
[patent_app_type] => new
[patent_app_number] => 10/340349
[patent_app_country] => US
[patent_app_date] => 2003-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7712
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20030110427.pdf
[firstpage_image] =>[orig_patent_app_number] => 10340349
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/340349 | Semiconductor test system storing pin calibration data in non-volatile memory | Jan 9, 2003 | Abandoned |
Array
(
[id] => 7293560
[patent_doc_number] => 20040111654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Memory device with debug mode'
[patent_app_type] => new
[patent_app_number] => 10/338343
[patent_app_country] => US
[patent_app_date] => 2003-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1356
[patent_no_of_claims] => 18
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[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0111/20040111654.pdf
[firstpage_image] =>[orig_patent_app_number] => 10338343
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338343 | Memory device with debug mode | Jan 7, 2003 | Abandoned |
Array
(
[id] => 7341664
[patent_doc_number] => 20040133827
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Internal data generation and compare via unused external pins'
[patent_app_type] => new
[patent_app_number] => 10/336140
[patent_app_country] => US
[patent_app_date] => 2003-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2608
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20040133827.pdf
[firstpage_image] =>[orig_patent_app_number] => 10336140
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/336140 | Internal data generation and compare via unused external pins | Jan 1, 2003 | Abandoned |
Array
(
[id] => 6763170
[patent_doc_number] => 20030126532
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-03
[patent_title] => 'Integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/330443
[patent_app_country] => US
[patent_app_date] => 2002-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5288
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20030126532.pdf
[firstpage_image] =>[orig_patent_app_number] => 10330443
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/330443 | Integrated circuit | Dec 26, 2002 | Abandoned |
Array
(
[id] => 6704688
[patent_doc_number] => 20030151422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-14
[patent_title] => 'Method for burn-in testing'
[patent_app_type] => new
[patent_app_number] => 10/248126
[patent_app_country] => US
[patent_app_date] => 2002-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3384
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0151/20030151422.pdf
[firstpage_image] =>[orig_patent_app_number] => 10248126
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/248126 | Method for burn-in testing | Dec 18, 2002 | Abandoned |
Array
(
[id] => 539983
[patent_doc_number] => 07188270
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-06
[patent_title] => 'Method and system for a disk fault tolerance in a disk array using rotating parity'
[patent_app_type] => utility
[patent_app_number] => 10/300981
[patent_app_country] => US
[patent_app_date] => 2002-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 10846
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 383
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/188/07188270.pdf
[firstpage_image] =>[orig_patent_app_number] => 10300981
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300981 | Method and system for a disk fault tolerance in a disk array using rotating parity | Nov 20, 2002 | Issued |
Array
(
[id] => 7477163
[patent_doc_number] => 20040098646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-20
[patent_title] => 'Method and apparatus to check the integrity of scan chain connectivity by traversing the test logic of the device'
[patent_app_type] => new
[patent_app_number] => 10/300513
[patent_app_country] => US
[patent_app_date] => 2002-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6613
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20040098646.pdf
[firstpage_image] =>[orig_patent_app_number] => 10300513
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300513 | Method and apparatus to check the integrity of scan chain connectivity by traversing the test logic of the device | Nov 19, 2002 | Abandoned |
Array
(
[id] => 6766987
[patent_doc_number] => 20030101387
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-29
[patent_title] => 'Apparatus and method for varying packet frame length'
[patent_app_type] => new
[patent_app_number] => 10/300025
[patent_app_country] => US
[patent_app_date] => 2002-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2901
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20030101387.pdf
[firstpage_image] =>[orig_patent_app_number] => 10300025
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300025 | Apparatus and method for varying packet frame length | Nov 19, 2002 | Abandoned |
Array
(
[id] => 598493
[patent_doc_number] => 07451363
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-11
[patent_title] => 'Semiconductor integrated circuit including memory macro'
[patent_app_type] => utility
[patent_app_number] => 10/300227
[patent_app_country] => US
[patent_app_date] => 2002-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 28011
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/451/07451363.pdf
[firstpage_image] =>[orig_patent_app_number] => 10300227
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300227 | Semiconductor integrated circuit including memory macro | Nov 18, 2002 | Issued |
Array
(
[id] => 6707313
[patent_doc_number] => 20030154047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-14
[patent_title] => 'Tester for mixed signal semiconductor device and method of testing semiconductor device using the same'
[patent_app_type] => new
[patent_app_number] => 10/300491
[patent_app_country] => US
[patent_app_date] => 2002-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3058
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0154/20030154047.pdf
[firstpage_image] =>[orig_patent_app_number] => 10300491
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300491 | Tester for mixed signal semiconductor device and method of testing semiconductor device using the same | Nov 18, 2002 | Abandoned |
Array
(
[id] => 7477172
[patent_doc_number] => 20040098655
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-20
[patent_title] => 'Rolling CRC scheme for improved error detection'
[patent_app_type] => new
[patent_app_number] => 10/300443
[patent_app_country] => US
[patent_app_date] => 2002-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 5743
[patent_no_of_claims] => 49
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20040098655.pdf
[firstpage_image] =>[orig_patent_app_number] => 10300443
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300443 | Rolling CRC scheme for improved error detection | Nov 18, 2002 | Abandoned |
Array
(
[id] => 290470
[patent_doc_number] => 07549096
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-06-16
[patent_title] => 'Methods and systems for tracking and playing back errors in a communications network'
[patent_app_type] => utility
[patent_app_number] => 10/299549
[patent_app_country] => US
[patent_app_date] => 2002-11-18
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/549/07549096.pdf
[firstpage_image] =>[orig_patent_app_number] => 10299549
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/299549 | Methods and systems for tracking and playing back errors in a communications network | Nov 17, 2002 | Issued |
Array
(
[id] => 7215387
[patent_doc_number] => 20050044471
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Error concealment apparatus and method'
[patent_app_type] => utility
[patent_app_number] => 10/494359
[patent_app_country] => US
[patent_app_date] => 2002-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] => publications/A1/0044/20050044471.pdf
[firstpage_image] =>[orig_patent_app_number] => 10494359
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/494359 | Error concealment apparatus and method | Nov 14, 2002 | Abandoned |
Array
(
[id] => 7449979
[patent_doc_number] => 20040268191
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Memory unit test'
[patent_app_type] => new
[patent_app_number] => 10/494794
[patent_app_country] => US
[patent_app_date] => 2004-05-05
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0268/20040268191.pdf
[firstpage_image] =>[orig_patent_app_number] => 10494794
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/494794 | Memory unit test | Oct 29, 2002 | Issued |
Array
(
[id] => 7063497
[patent_doc_number] => 20050005212
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Electronic component with output buffer control'
[patent_app_type] => utility
[patent_app_number] => 10/494550
[patent_app_country] => US
[patent_app_date] => 2002-10-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0005/20050005212.pdf
[firstpage_image] =>[orig_patent_app_number] => 10494550
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/494550 | Electronic component with output buffer control | Oct 27, 2002 | Abandoned |
Array
(
[id] => 6974017
[patent_doc_number] => 20050039093
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Automatic scan-based testing of complex integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/491658
[patent_app_country] => US
[patent_app_date] => 2002-10-01
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0039/20050039093.pdf
[firstpage_image] =>[orig_patent_app_number] => 10491658
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/491658 | Automatic scan-based testing of complex integrated circuits | Sep 30, 2002 | Abandoned |
Array
(
[id] => 7271467
[patent_doc_number] => 20040059985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Method and apparatus for tracking address of memory errors'
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[patent_app_number] => 10/254169
[patent_app_country] => US
[patent_app_date] => 2002-09-25
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[pdf_file] => publications/A1/0059/20040059985.pdf
[firstpage_image] =>[orig_patent_app_number] => 10254169
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/254169 | Method and apparatus for tracking address of memory errors | Sep 24, 2002 | Abandoned |
Array
(
[id] => 6868791
[patent_doc_number] => 20030081480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-01
[patent_title] => 'Semiconductor memory device and its data writing method'
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[pdf_file] => publications/A1/0081/20030081480.pdf
[firstpage_image] =>[orig_patent_app_number] => 10247356
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247356 | Semiconductor memory device and its data writing method | Sep 19, 2002 | Issued |
Array
(
[id] => 6844576
[patent_doc_number] => 20030149923
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-07
[patent_title] => 'Semiconductor device testing method and test system'
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[pdf_file] => publications/A1/0149/20030149923.pdf
[firstpage_image] =>[orig_patent_app_number] => 10247686
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247686 | Semiconductor device testing method and test system | Sep 19, 2002 | Abandoned |
Array
(
[id] => 6661153
[patent_doc_number] => 20030135797
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-17
[patent_title] => 'Method and apparatus for enhancing the transmission of error in the IEEE 802.11e systems'
[patent_app_type] => new
[patent_app_number] => 10/247200
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0135/20030135797.pdf
[firstpage_image] =>[orig_patent_app_number] => 10247200
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247200 | Method and apparatus for enhancing the transmission of error in the IEEE 802.11e systems | Sep 18, 2002 | Abandoned |