
Austin Murata
Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )
| Most Active Art Unit | 1712 |
| Art Unit(s) | 1712, 1792 |
| Total Applications | 853 |
| Issued Applications | 467 |
| Pending Applications | 93 |
| Abandoned Applications | 315 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 58756
[patent_doc_number] => 07770085
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-03
[patent_title] => 'Replacement messages for identifying and preventing errors during the transmission of real time-critical data'
[patent_app_type] => utility
[patent_app_number] => 10/490534
[patent_app_country] => US
[patent_app_date] => 2002-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2410
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/770/07770085.pdf
[firstpage_image] =>[orig_patent_app_number] => 10490534
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/490534 | Replacement messages for identifying and preventing errors during the transmission of real time-critical data | Sep 11, 2002 | Issued |
Array
(
[id] => 7123860
[patent_doc_number] => 20050015689
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Electronic component and method for measuring its qualification'
[patent_app_type] => utility
[patent_app_number] => 10/489685
[patent_app_country] => US
[patent_app_date] => 2002-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4109
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0015/20050015689.pdf
[firstpage_image] =>[orig_patent_app_number] => 10489685
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/489685 | Electronic component and method for measuring its qualification | Aug 29, 2002 | Abandoned |
Array
(
[id] => 193006
[patent_doc_number] => 07644333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'Restartable logic BIST controller'
[patent_app_type] => utility
[patent_app_number] => 10/194377
[patent_app_country] => US
[patent_app_date] => 2002-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 6825
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/644/07644333.pdf
[firstpage_image] =>[orig_patent_app_number] => 10194377
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/194377 | Restartable logic BIST controller | Jul 11, 2002 | Issued |
Array
(
[id] => 6857802
[patent_doc_number] => 20030131303
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-10
[patent_title] => 'Reverse transmission apparatus and method for improving transmission throughput in a data communication system'
[patent_app_type] => new
[patent_app_number] => 10/193785
[patent_app_country] => US
[patent_app_date] => 2002-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 11524
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20030131303.pdf
[firstpage_image] =>[orig_patent_app_number] => 10193785
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/193785 | Reverse transmission apparatus and method for improving transmission throughput in a data communication system | Jul 11, 2002 | Abandoned |
Array
(
[id] => 508790
[patent_doc_number] => 07210089
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-24
[patent_title] => 'Communication system employing turbo codes and a hybrid automatic repeat request scheme'
[patent_app_type] => utility
[patent_app_number] => 10/193144
[patent_app_country] => US
[patent_app_date] => 2002-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4875
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/210/07210089.pdf
[firstpage_image] =>[orig_patent_app_number] => 10193144
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/193144 | Communication system employing turbo codes and a hybrid automatic repeat request scheme | Jul 11, 2002 | Issued |
Array
(
[id] => 7601871
[patent_doc_number] => 07237175
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-26
[patent_title] => 'Memory circuit'
[patent_app_type] => utility
[patent_app_number] => 10/193319
[patent_app_country] => US
[patent_app_date] => 2002-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3990
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 303
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/237/07237175.pdf
[firstpage_image] =>[orig_patent_app_number] => 10193319
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/193319 | Memory circuit | Jul 11, 2002 | Issued |
Array
(
[id] => 560703
[patent_doc_number] => 07178091
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-02-13
[patent_title] => 'Reed solomon encoder'
[patent_app_type] => utility
[patent_app_number] => 10/192761
[patent_app_country] => US
[patent_app_date] => 2002-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4722
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/178/07178091.pdf
[firstpage_image] =>[orig_patent_app_number] => 10192761
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/192761 | Reed solomon encoder | Jul 9, 2002 | Issued |
Array
(
[id] => 6837455
[patent_doc_number] => 20030034795
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-20
[patent_title] => 'Delayed flash clear scan flip-flop to be implemented in complex integrated circuit designs'
[patent_app_type] => new
[patent_app_number] => 10/191668
[patent_app_country] => US
[patent_app_date] => 2002-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3872
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20030034795.pdf
[firstpage_image] =>[orig_patent_app_number] => 10191668
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/191668 | Delayed flash clear scan flip-flop to be implemented in complex integrated circuit designs | Jul 8, 2002 | Abandoned |
Array
(
[id] => 7372930
[patent_doc_number] => 20040006733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-08
[patent_title] => 'Method for repairing received signal and equalizer'
[patent_app_type] => new
[patent_app_number] => 10/189237
[patent_app_country] => US
[patent_app_date] => 2002-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4499
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 12
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20040006733.pdf
[firstpage_image] =>[orig_patent_app_number] => 10189237
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/189237 | Method for repairing received signal and equalizer | Jul 4, 2002 | Abandoned |
Array
(
[id] => 7372916
[patent_doc_number] => 20040006729
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-08
[patent_title] => 'Hierarchical test methodology for multi-core chips'
[patent_app_type] => new
[patent_app_number] => 10/189870
[patent_app_country] => US
[patent_app_date] => 2002-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5035
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20040006729.pdf
[firstpage_image] =>[orig_patent_app_number] => 10189870
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/189870 | Hierarchical test methodology for multi-core chips | Jul 2, 2002 | Abandoned |
Array
(
[id] => 6656443
[patent_doc_number] => 20030009720
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-09
[patent_title] => 'Address information detecting apparatus and address information detecting method'
[patent_app_type] => new
[patent_app_number] => 10/190363
[patent_app_country] => US
[patent_app_date] => 2002-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 11723
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20030009720.pdf
[firstpage_image] =>[orig_patent_app_number] => 10190363
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/190363 | Address information detecting apparatus and address information detecting method | Jul 2, 2002 | Issued |
Array
(
[id] => 7260476
[patent_doc_number] => 20050076275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-07
[patent_title] => 'Integraged circuit and method for testing the integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 10/480750
[patent_app_country] => US
[patent_app_date] => 2002-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4471
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20050076275.pdf
[firstpage_image] =>[orig_patent_app_number] => 10480750
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/480750 | Integraged circuit and method for testing the integrated circuit | Jun 9, 2002 | Abandoned |
Array
(
[id] => 7358280
[patent_doc_number] => 20040249987
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Integrated digital circuit and method for operating an integrated digital circuit'
[patent_app_type] => new
[patent_app_number] => 10/479929
[patent_app_country] => US
[patent_app_date] => 2004-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4710
[patent_no_of_claims] => 2
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20040249987.pdf
[firstpage_image] =>[orig_patent_app_number] => 10479929
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/479929 | Integrated digital circuit and a method for operating a digital circuit | Jun 5, 2002 | Issued |
Array
(
[id] => 7418961
[patent_doc_number] => 20040177314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Digital system and a method for error detection thereof'
[patent_app_type] => new
[patent_app_number] => 10/479089
[patent_app_country] => US
[patent_app_date] => 2003-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3117
[patent_no_of_claims] => 10
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0177/20040177314.pdf
[firstpage_image] =>[orig_patent_app_number] => 10479089
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/479089 | Digital system and a method for error detection thereof | May 29, 2002 | Issued |
| 10/070848 | Error control method and apparatus | May 8, 2002 | Abandoned |
Array
(
[id] => 6509394
[patent_doc_number] => 20020191606
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-19
[patent_title] => 'Network system-wide error handling utilizing control bit modification'
[patent_app_type] => new
[patent_app_number] => 10/142022
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 7086
[patent_no_of_claims] => 50
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0191/20020191606.pdf
[firstpage_image] =>[orig_patent_app_number] => 10142022
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/142022 | Network system-wide error handling utilizing control bit modification | May 8, 2002 | Abandoned |
Array
(
[id] => 6648187
[patent_doc_number] => 20030212932
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Remote diagnostic packets'
[patent_app_type] => new
[patent_app_number] => 10/142033
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5141
[patent_no_of_claims] => 23
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20030212932.pdf
[firstpage_image] =>[orig_patent_app_number] => 10142033
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/142033 | Remote diagnostic packets | May 8, 2002 | Abandoned |
Array
(
[id] => 6648224
[patent_doc_number] => 20030212939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Method and apparatus for selecting the operational mode of an integrated circuit'
[patent_app_type] => new
[patent_app_number] => 10/141752
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2908
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20030212939.pdf
[firstpage_image] =>[orig_patent_app_number] => 10141752
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/141752 | Method and apparatus for selecting the operational mode of an integrated circuit | May 8, 2002 | Abandoned |
Array
(
[id] => 6648219
[patent_doc_number] => 20030212938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Method and apparatus for generating electronic test and data structure'
[patent_app_type] => new
[patent_app_number] => 10/141719
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0212/20030212938.pdf
[firstpage_image] =>[orig_patent_app_number] => 10141719
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/141719 | Method and apparatus for generating electronic test and data structure | May 8, 2002 | Issued |
Array
(
[id] => 513678
[patent_doc_number] => 07206985
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-17
[patent_title] => 'Method and apparatus for calibrating a test system for an integrated semiconductor circuit'
[patent_app_type] => utility
[patent_app_number] => 10/139835
[patent_app_country] => US
[patent_app_date] => 2002-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/206/07206985.pdf
[firstpage_image] =>[orig_patent_app_number] => 10139835
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/139835 | Method and apparatus for calibrating a test system for an integrated semiconductor circuit | May 6, 2002 | Issued |