Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19741831 [patent_doc_number] => 12218684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Layered semi parallel LDPC decoder system having single permutation network [patent_app_type] => utility [patent_app_number] => 17/792601 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5637 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 508 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17792601 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/792601
Layered semi parallel LDPC decoder system having single permutation network Nov 14, 2021 Issued
Array ( [id] => 18506213 [patent_doc_number] => 11704027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Optimizing recovery of recurrent blocks using bloom filter [patent_app_type] => utility [patent_app_number] => 17/454711 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6224 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454711 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454711
Optimizing recovery of recurrent blocks using bloom filter Nov 11, 2021 Issued
Array ( [id] => 17416845 [patent_doc_number] => 20220051749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => RECOVERY MANAGEMENT OF RETIRED SUPER MANAGEMENT UNITS [patent_app_type] => utility [patent_app_number] => 17/452717 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452717
Recovery management of retired super management units Oct 27, 2021 Issued
Array ( [id] => 18781995 [patent_doc_number] => 11823760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => System and method for data integrity in memory systems that include quasi-volatile memory circuits [patent_app_type] => utility [patent_app_number] => 17/512449 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4775 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512449
System and method for data integrity in memory systems that include quasi-volatile memory circuits Oct 26, 2021 Issued
Array ( [id] => 18541629 [patent_doc_number] => 20230246745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-03 [patent_title] => COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/023970 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18023970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/023970
Communication system Oct 13, 2021 Issued
Array ( [id] => 18280442 [patent_doc_number] => 20230095914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/485211 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485211
TEST AND DEBUG SUPPORT WITH HBI CHIPLET ARCHITECTURE Sep 23, 2021 Abandoned
Array ( [id] => 18593133 [patent_doc_number] => 11742042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Program pulse control using environmental parameters [patent_app_type] => utility [patent_app_number] => 17/474539 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7082 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17474539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/474539
Program pulse control using environmental parameters Sep 13, 2021 Issued
Array ( [id] => 18840598 [patent_doc_number] => 11848684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Method, system, device and storage medium for constructing base matrix of PBRL LDPC code [patent_app_type] => utility [patent_app_number] => 17/445732 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 13763 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445732
Method, system, device and storage medium for constructing base matrix of PBRL LDPC code Aug 23, 2021 Issued
Array ( [id] => 17854935 [patent_doc_number] => 20220284978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/404558 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404558
MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME Aug 16, 2021 Abandoned
Array ( [id] => 18744293 [patent_doc_number] => 20230353282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => DATA SENDING AND RECEIVING METHODS AND TERMINALS, SYSTEM, ELECTRONIC DEVICE AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/245385 [patent_app_country] => US [patent_app_date] => 2021-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18245385 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/245385
DATA SENDING AND RECEIVING METHODS AND TERMINALS, SYSTEM, ELECTRONIC DEVICE AND STORAGE MEDIUM Aug 8, 2021 Abandoned
Array ( [id] => 19123397 [patent_doc_number] => 11967391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => System and method for testing multicore SSD firmware based on preconditions generation [patent_app_type] => utility [patent_app_number] => 17/396185 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6915 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396185
System and method for testing multicore SSD firmware based on preconditions generation Aug 5, 2021 Issued
Array ( [id] => 17401670 [patent_doc_number] => 20220043760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => METHOD FOR TUNING AN EXTERNAL MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 17/390807 [patent_app_country] => US [patent_app_date] => 2021-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/390807
Method for tuning an external memory interface Jul 29, 2021 Issued
Array ( [id] => 18206091 [patent_doc_number] => 11588502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 64-symbol mapping, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 17/386373 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5806 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386373 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386373
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 64-symbol mapping, and bit interleaving method using same Jul 26, 2021 Issued
Array ( [id] => 19079278 [patent_doc_number] => 11948653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Early error detection and automatic correction techniques for storage elements to improve reliability [patent_app_type] => utility [patent_app_number] => 17/381143 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7065 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/381143
Early error detection and automatic correction techniques for storage elements to improve reliability Jul 19, 2021 Issued
Array ( [id] => 18220103 [patent_doc_number] => 11595060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Method and apparatus for decoding low-density parity-check code [patent_app_type] => utility [patent_app_number] => 17/377643 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8533 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377643
Method and apparatus for decoding low-density parity-check code Jul 15, 2021 Issued
Array ( [id] => 19044743 [patent_doc_number] => 11933843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Techniques to enable integrated circuit debug across low power states [patent_app_type] => utility [patent_app_number] => 17/377264 [patent_app_country] => US [patent_app_date] => 2021-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10408 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377264
Techniques to enable integrated circuit debug across low power states Jul 14, 2021 Issued
Array ( [id] => 19741906 [patent_doc_number] => 12218759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Electronic device, communication method and storage medium [patent_app_type] => utility [patent_app_number] => 18/008683 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 19466 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 464 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18008683 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/008683
Electronic device, communication method and storage medium Jul 5, 2021 Issued
Array ( [id] => 19329475 [patent_doc_number] => 12047171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Selection of pivot positions for linear network codes [patent_app_type] => utility [patent_app_number] => 18/245234 [patent_app_country] => US [patent_app_date] => 2021-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4742 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18245234 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/245234
Selection of pivot positions for linear network codes Jul 4, 2021 Issued
Array ( [id] => 18175664 [patent_doc_number] => 11575390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder [patent_app_type] => utility [patent_app_number] => 17/367195 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 15121 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367195 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367195
Low-latency segmented quasi-cyclic low-density parity-check (QC-LDPC) decoder Jul 1, 2021 Issued
Array ( [id] => 17173854 [patent_doc_number] => 20210327525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES [patent_app_type] => utility [patent_app_number] => 17/364647 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364647
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES Jun 29, 2021 Abandoned
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