Search

Austin Murata

Examiner (ID: 10394, Phone: (571)270-5596 , Office: P/1712 )

Most Active Art Unit
1712
Art Unit(s)
1712, 1792
Total Applications
853
Issued Applications
467
Pending Applications
93
Abandoned Applications
315

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18471824 [patent_doc_number] => 20230206110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => QUANTUM REPEATERS FOR CONCATENATED QUANTUM ERROR CORRECTION, AND ASSOCIATED METHODS [patent_app_type] => utility [patent_app_number] => 18/000074 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18000074 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/000074
Quantum repeaters for concatenated quantum error correction, and associated methods Jun 3, 2021 Issued
Array ( [id] => 19421543 [patent_doc_number] => 20240297667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => METHOD AND ARRANGEMENTS FOR SUPPORTING FORWARD ERROR CORRECTION DECODING OF A WORD [patent_app_type] => utility [patent_app_number] => 18/566195 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18566195 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/566195
METHOD AND ARRANGEMENTS FOR SUPPORTING FORWARD ERROR CORRECTION DECODING OF A WORD Jun 1, 2021 Pending
Array ( [id] => 18041086 [patent_doc_number] => 20220385303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => Multi-Rate ECC Parity For Fast SLC Read [patent_app_type] => utility [patent_app_number] => 17/331346 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331346 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331346
Multi-rate ECC parity for fast SLC read May 25, 2021 Issued
Array ( [id] => 18356746 [patent_doc_number] => 11645147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Generating error checking data for error detection during modification of data in a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/324845 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/324845
Generating error checking data for error detection during modification of data in a memory sub-system May 18, 2021 Issued
Array ( [id] => 19843259 [patent_doc_number] => 12255667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Method and apparatus for performing channel coding of UE and base station in wireless communication system [patent_app_type] => utility [patent_app_number] => 18/029351 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 19451 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18029351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/029351
Method and apparatus for performing channel coding of UE and base station in wireless communication system May 13, 2021 Issued
Array ( [id] => 17055571 [patent_doc_number] => 20210265005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => MEMORY CONTROLLER OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/317506 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317506
MEMORY CONTROLLER OPERATING METHOD OF MEMORY CONTROLLER AND MEMORY SYSTEM May 10, 2021 Abandoned
Array ( [id] => 18343360 [patent_doc_number] => 11640843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Semiconductor memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/220284 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5984 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/220284
Semiconductor memory device and operating method thereof Mar 31, 2021 Issued
Array ( [id] => 17971989 [patent_doc_number] => 11489544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Fast CRC computation circuit using an on-the-fly reconfigurable generator polynomial [patent_app_type] => utility [patent_app_number] => 17/217640 [patent_app_country] => US [patent_app_date] => 2021-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3308 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217640 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/217640
Fast CRC computation circuit using an on-the-fly reconfigurable generator polynomial Mar 29, 2021 Issued
Array ( [id] => 17887454 [patent_doc_number] => 20220302932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => ERROR RECOVERY USING ADAPTIVE LLR LOOKUP TABLE [patent_app_type] => utility [patent_app_number] => 17/204079 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204079 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204079
Error recovery using adaptive LLR lookup table Mar 16, 2021 Issued
Array ( [id] => 18464923 [patent_doc_number] => 11689224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Error correction device and method for generating syndromes and partial coefficient information in a parallel [patent_app_type] => utility [patent_app_number] => 17/199803 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 7869 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199803
Error correction device and method for generating syndromes and partial coefficient information in a parallel Mar 11, 2021 Issued
Array ( [id] => 17530593 [patent_doc_number] => 11303302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Erasure code calculation method [patent_app_type] => utility [patent_app_number] => 17/199093 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7162 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1470 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199093
Erasure code calculation method Mar 10, 2021 Issued
Array ( [id] => 17925702 [patent_doc_number] => 11468962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Performing memory testing using error correction code values [patent_app_type] => utility [patent_app_number] => 17/190800 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8108 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190800 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190800
Performing memory testing using error correction code values Mar 2, 2021 Issued
Array ( [id] => 17970078 [patent_doc_number] => 11487611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => LDPC encoding for memory cells with arbitrary number of levels [patent_app_type] => utility [patent_app_number] => 17/183153 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183153
LDPC encoding for memory cells with arbitrary number of levels Feb 22, 2021 Issued
Array ( [id] => 18032687 [patent_doc_number] => 11515892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Transmitter and parity permutation method thereof [patent_app_type] => utility [patent_app_number] => 17/180969 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 31618 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180969
Transmitter and parity permutation method thereof Feb 21, 2021 Issued
Array ( [id] => 17510084 [patent_doc_number] => 20220103188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => DATA STORAGE DEVICE CHANNEL ENCODING CURRENT DATA USING REDUNDANCY BITS GENERATED OVER PRECEDING DATA [patent_app_type] => utility [patent_app_number] => 17/179542 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179542
Data storage device channel encoding current data using redundancy bits generated over preceding data Feb 18, 2021 Issued
Array ( [id] => 17956893 [patent_doc_number] => 11483012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Decoding system and method for low latency bit-flipping successive cancellation decoding for polar codes [patent_app_type] => utility [patent_app_number] => 17/178356 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4753 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178356
Decoding system and method for low latency bit-flipping successive cancellation decoding for polar codes Feb 17, 2021 Issued
Array ( [id] => 16859177 [patent_doc_number] => 20210159922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => PERFORMING A DECODING OPERATION TO SIMULATE SWITCHING A BIT OF AN IDENTIFIED SET OF BITS OF A DATA BLOCK [patent_app_type] => utility [patent_app_number] => 17/248726 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17248726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/248726
Performing a decoding operation to simulate switching a bit of an identified set of bits of a data block Feb 3, 2021 Issued
Array ( [id] => 17699990 [patent_doc_number] => 11373722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 17/149495 [patent_app_country] => US [patent_app_date] => 2021-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 13451 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149495
Memory device Jan 13, 2021 Issued
Array ( [id] => 17729419 [patent_doc_number] => 11385806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-12 [patent_title] => Methods and systems for efficient erasure-coded storage systems [patent_app_type] => utility [patent_app_number] => 17/140108 [patent_app_country] => US [patent_app_date] => 2021-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 21364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140108
Methods and systems for efficient erasure-coded storage systems Jan 2, 2021 Issued
Array ( [id] => 18030705 [patent_doc_number] => 11513894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Hard decoding methods in data storage devices [patent_app_type] => utility [patent_app_number] => 17/135722 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 17438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135722
Hard decoding methods in data storage devices Dec 27, 2020 Issued
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