Austin Murata

Array ( [id] => 16782651 [patent_doc_number] => 20210119730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => FORWARD ERROR CORRECTION AND CYCLIC REDUNDANCY CHECK MECHANISMS FOR LATENCY-CRITICAL COHERENCY AND MEMORY INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/134240 [patent_app_country] => US [patent_app_date] => 2020-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16858139 [patent_doc_number] => 20210158884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY ABNORMALITY DETERMINATION SYSTEM [patent_app_type] => utility [patent_app_number] => 16/951537 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951537 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19415496 [patent_doc_number] => 12081340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Hybrid automatic repeat request acknowledgement codebook determination method and device [patent_app_type] => utility [patent_app_number] => 17/775348 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 14985 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17775348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17144988 [patent_doc_number] => 20210313001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => MEMORY DEVICE AND TEST METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/073682 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18775369 [patent_doc_number] => 20230370204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => TERMINAL AND COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/246133 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18246133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17535454 [patent_doc_number] => 20220114063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => TECHNIQUES FOR FAULT DETECTION IN WIRELESS COMMUNICATIONS SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/069437 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17515432 [patent_doc_number] => 11294580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 17/033077 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 38 [patent_no_of_words] => 16034 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17607802 [patent_doc_number] => 11336297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => DMA transfer apparatus, method of controlling the same, communication apparatus, method of controlling the same, and non-transitory computer-readable storage medium [patent_app_type] => utility [patent_app_number] => 17/029248 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17220 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18840602 [patent_doc_number] => 11848688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Decoding method and device, apparatus, and storage medium [patent_app_type] => utility [patent_app_number] => 17/778932 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 9373 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17778932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18292177 [patent_doc_number] => 11621050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Semiconductor memory devices and repair methods of the semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 17/024396 [patent_app_country] => US [patent_app_date] => 2020-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13639 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17423112 [patent_doc_number] => 11256566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Enhanced bit flipping scheme [patent_app_type] => utility [patent_app_number] => 17/016004 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 17428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17016004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16528523 [patent_doc_number] => 20200402604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => Apparatus and Method for Testing Storage Device in Power Interruptions [patent_app_type] => utility [patent_app_number] => 17/012368 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17070428 [patent_doc_number] => 20210272645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => MEMORY DEVICE AND METHOD FOR REDUCING BAD BLOCK TEST TIME [patent_app_type] => utility [patent_app_number] => 17/010238 [patent_app_country] => US [patent_app_date] => 2020-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17010238 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17848626 [patent_doc_number] => 11438015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Two-level error correcting code with sharing of check-bits [patent_app_type] => utility [patent_app_number] => 16/925361 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17340139 [patent_doc_number] => 20220006470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => Apparatuses, Devices, Methods and Computer Programs for Generating and Employing LDPC Matrices [patent_app_type] => utility [patent_app_number] => 16/920812 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17803104 [patent_doc_number] => 11417413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Semiconductor memory apparatus and method for reading the same [patent_app_type] => utility [patent_app_number] => 16/920371 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6999 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18023261 [patent_doc_number] => 20220374760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => METHOD FOR SENDING CLASSICAL DATA IN QUANTUM INFORMATION PROCESSING SYSTEMS AND CORRESPONDING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/624448 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17624448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16811828 [patent_doc_number] => 20210134383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/918765 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16314466 [patent_doc_number] => 20200293204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => NONVOLATILE MEMORY DEVICE, METHOD OF OPERATING NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/892512 [patent_app_country] => US [patent_app_date] => 2020-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16892512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17247871 [patent_doc_number] => 20210367616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => DESCRAMBLER FOR MEMORY SYSTEMS AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/879492 [patent_app_country] => US [patent_app_date] => 2020-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16879492 [rel_patent_id] =>[rel_patent_doc_number] =>)