Search

Avinash A. Savani

Examiner (ID: 192)

Most Active Art Unit
3749
Art Unit(s)
3743, 3749, 3762
Total Applications
1428
Issued Applications
1004
Pending Applications
115
Abandoned Applications
348

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16964257 [patent_doc_number] => 20210215756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => Method, Apparatus and Storage Medium for Testing Chip, and Chip Thereof [patent_app_type] => utility [patent_app_number] => 17/213672 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213672 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213672
Method, apparatus and storage medium for testing chip, and chip thereof Mar 25, 2021 Issued
Array ( [id] => 18048679 [patent_doc_number] => 11522642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Intelligent packet repetition in mobile satellite service (MSS) links to overcome channel blockages [patent_app_type] => utility [patent_app_number] => 17/211115 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5800 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211115
Intelligent packet repetition in mobile satellite service (MSS) links to overcome channel blockages Mar 23, 2021 Issued
Array ( [id] => 16979078 [patent_doc_number] => 20210223315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => SYSTEM-ON-CHIP FOR AT-SPEED TEST OF LOGIC CIRCUIT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/206288 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206288 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/206288
System-on-chip for AT-SPEED test of logic circuit and operating method thereof Mar 18, 2021 Issued
Array ( [id] => 19583230 [patent_doc_number] => 12149366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Communication device and communication system for retransmission control [patent_app_type] => utility [patent_app_number] => 17/906724 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 13436 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17906724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/906724
Communication device and communication system for retransmission control Mar 17, 2021 Issued
Array ( [id] => 17884889 [patent_doc_number] => 20220300366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => ADAPTIVE BACKGROUND SCANS IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/205545 [patent_app_country] => US [patent_app_date] => 2021-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17205545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/205545
Adaptive background scans in a memory sub-system Mar 17, 2021 Issued
Array ( [id] => 18262118 [patent_doc_number] => 11609819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => NAND device mixed parity management [patent_app_type] => utility [patent_app_number] => 17/201754 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11391 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201754
NAND device mixed parity management Mar 14, 2021 Issued
Array ( [id] => 17171787 [patent_doc_number] => 20210325457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => SCAN OUTPUT FLIP-FLOP WITH POWER SAVING FEATURE [patent_app_type] => utility [patent_app_number] => 17/198276 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198276
Scan output flip-flop with power saving feature Mar 10, 2021 Issued
Array ( [id] => 16886805 [patent_doc_number] => 20210173001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => INTERPOSER INSTRUMENTATION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 17/181402 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181402 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181402
Interposer instrumentation method and apparatus Feb 21, 2021 Issued
Array ( [id] => 17846037 [patent_doc_number] => 11435401 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-06 [patent_title] => Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip [patent_app_type] => utility [patent_app_number] => 17/181486 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 17717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181486
Timed transition cell-aware ATPG using fault rule files and SDF for testing an IC chip Feb 21, 2021 Issued
Array ( [id] => 17824534 [patent_doc_number] => 11429482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Systems and methods for correcting data errors in memory [patent_app_type] => utility [patent_app_number] => 17/178651 [patent_app_country] => US [patent_app_date] => 2021-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178651
Systems and methods for correcting data errors in memory Feb 17, 2021 Issued
Array ( [id] => 18206172 [patent_doc_number] => 11588584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Short latency fast retransmission triggering [patent_app_type] => utility [patent_app_number] => 17/174916 [patent_app_country] => US [patent_app_date] => 2021-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15103 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17174916 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/174916
Short latency fast retransmission triggering Feb 11, 2021 Issued
Array ( [id] => 17876689 [patent_doc_number] => 11448697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Apparatus for device access port selection [patent_app_type] => utility [patent_app_number] => 17/171443 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 58 [patent_no_of_words] => 17588 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171443
Apparatus for device access port selection Feb 8, 2021 Issued
Array ( [id] => 17113286 [patent_doc_number] => 20210293883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => ERROR RATE MEASURING APPARATUS AND DATA DIVISION DISPLAY METHOD [patent_app_type] => utility [patent_app_number] => 17/170137 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170137
Error rate measuring apparatus and data division display method Feb 7, 2021 Issued
Array ( [id] => 16859175 [patent_doc_number] => 20210159920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 17/165614 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165614 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165614
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 16-symbol mapping, and bit interleaving method using same Feb 1, 2021 Issued
Array ( [id] => 17743709 [patent_doc_number] => 11391769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Integrated circuit die test architecture [patent_app_type] => utility [patent_app_number] => 17/162025 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 5025 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162025
Integrated circuit die test architecture Jan 28, 2021 Issued
Array ( [id] => 17969404 [patent_doc_number] => 11486928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Electronic circuit and corresponding method of testing electronic circuits [patent_app_type] => utility [patent_app_number] => 17/159511 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4436 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159511
Electronic circuit and corresponding method of testing electronic circuits Jan 26, 2021 Issued
Array ( [id] => 16851443 [patent_doc_number] => 20210152188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => DATA PROCESSING DEVICE AND DATA PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/158839 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 53458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 487 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158839 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158839
Data processing device and data processing method Jan 25, 2021 Issued
Array ( [id] => 17714633 [patent_doc_number] => 11378622 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-05 [patent_title] => Methods and systems for single-event upset fault injection testing [patent_app_type] => utility [patent_app_number] => 17/141872 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141872
Methods and systems for single-event upset fault injection testing Jan 4, 2021 Issued
Array ( [id] => 17940269 [patent_doc_number] => 11474722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Non-volatile memory including selective error correction [patent_app_type] => utility [patent_app_number] => 17/139526 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17139526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/139526
Non-volatile memory including selective error correction Dec 30, 2020 Issued
Array ( [id] => 16917770 [patent_doc_number] => 20210190862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SELF-TEST OF AN ASYNCHRONOUS CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/136198 [patent_app_country] => US [patent_app_date] => 2020-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17136198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/136198
Self-test of an asynchronous circuit Dec 28, 2020 Issued
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