Search

Awat M. Salih

Examiner (ID: 18788, Phone: (571)270-5601 , Office: P/2845 )

Most Active Art Unit
2845
Art Unit(s)
2845
Total Applications
569
Issued Applications
470
Pending Applications
50
Abandoned Applications
69

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5145608 [patent_doc_number] => 20070045662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'SUBSTRATE FOR FILM GROWTH OF GROUP III NITRIDES, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/467319 [patent_app_country] => US [patent_app_date] => 2006-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045662.pdf [firstpage_image] =>[orig_patent_app_number] => 11467319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/467319
SUBSTRATE FOR FILM GROWTH OF GROUP III NITRIDES, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE USING THE SAME Aug 24, 2006 Abandoned
Array ( [id] => 4768764 [patent_doc_number] => 20080054420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 11/466539 [patent_app_country] => US [patent_app_date] => 2006-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2125 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054420.pdf [firstpage_image] =>[orig_patent_app_number] => 11466539 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466539
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURE Aug 22, 2006 Abandoned
Array ( [id] => 4768765 [patent_doc_number] => 20080054421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTERLOCK' [patent_app_type] => utility [patent_app_number] => 11/466748 [patent_app_country] => US [patent_app_date] => 2006-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054421.pdf [firstpage_image] =>[orig_patent_app_number] => 11466748 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466748
Integrated circuit package system with interlock Aug 22, 2006 Issued
Array ( [id] => 9184434 [patent_doc_number] => 08624372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-07 [patent_title] => 'Semiconductor component comprising an interposer substrate' [patent_app_type] => utility [patent_app_number] => 11/466279 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6954 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11466279 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466279
Semiconductor component comprising an interposer substrate Aug 21, 2006 Issued
Array ( [id] => 143047 [patent_doc_number] => 07692210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-06 [patent_title] => 'Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same' [patent_app_type] => utility [patent_app_number] => 11/466309 [patent_app_country] => US [patent_app_date] => 2006-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4682 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/692/07692210.pdf [firstpage_image] =>[orig_patent_app_number] => 11466309 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/466309
Intermeshed guard bands for multiple voltage supply structures on an integrated circuit, and methods of making same Aug 21, 2006 Issued
Array ( [id] => 5145629 [patent_doc_number] => 20070045683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'LIGHT REFLECTIVITY CONTROLLED PHOTODIODE CELL, AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/465898 [patent_app_country] => US [patent_app_date] => 2006-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6398 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045683.pdf [firstpage_image] =>[orig_patent_app_number] => 11465898 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/465898
LIGHT REFLECTIVITY CONTROLLED PHOTODIODE CELL, AND METHOD OF MANUFACTURING THE SAME Aug 20, 2006 Abandoned
Array ( [id] => 229200 [patent_doc_number] => 07602015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Process to control semiconductor wafer yield' [patent_app_type] => utility [patent_app_number] => 11/464619 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1441 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602015.pdf [firstpage_image] =>[orig_patent_app_number] => 11464619 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/464619
Process to control semiconductor wafer yield Aug 14, 2006 Issued
Array ( [id] => 4997613 [patent_doc_number] => 20070040247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-22 [patent_title] => 'Leadframe package with dual lead configurations' [patent_app_type] => utility [patent_app_number] => 11/503269 [patent_app_country] => US [patent_app_date] => 2006-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6088 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20070040247.pdf [firstpage_image] =>[orig_patent_app_number] => 11503269 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/503269
Leadframe package with dual lead configurations Aug 13, 2006 Abandoned
Array ( [id] => 1076898 [patent_doc_number] => 07615410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Chip-sized flip-chip semiconductor package and method for making the same' [patent_app_type] => utility [patent_app_number] => 11/456978 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3046 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615410.pdf [firstpage_image] =>[orig_patent_app_number] => 11456978 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/456978
Chip-sized flip-chip semiconductor package and method for making the same Jul 11, 2006 Issued
Array ( [id] => 5622870 [patent_doc_number] => 20060261375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Power Semiconductor Component with Plate Capacitor Structure' [patent_app_type] => utility [patent_app_number] => 11/382838 [patent_app_country] => US [patent_app_date] => 2006-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7267 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261375.pdf [firstpage_image] =>[orig_patent_app_number] => 11382838 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/382838
Power semiconductor component with plate capacitor structure May 10, 2006 Issued
Array ( [id] => 5082880 [patent_doc_number] => 20070272931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'Methods, devices and systems producing illumination and effects' [patent_app_type] => utility [patent_app_number] => 11/418089 [patent_app_country] => US [patent_app_date] => 2006-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1424 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0272/20070272931.pdf [firstpage_image] =>[orig_patent_app_number] => 11418089 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/418089
Methods, devices and systems producing illumination and effects May 4, 2006 Abandoned
Array ( [id] => 5730327 [patent_doc_number] => 20060255441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Physical quantity sensor device' [patent_app_type] => utility [patent_app_number] => 11/417109 [patent_app_country] => US [patent_app_date] => 2006-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7921 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20060255441.pdf [firstpage_image] =>[orig_patent_app_number] => 11417109 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/417109
Physical quantity sensor device May 3, 2006 Abandoned
Array ( [id] => 5031688 [patent_doc_number] => 20070096227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Wafer level package for surface acoustic wave device and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/415099 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4452 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20070096227.pdf [firstpage_image] =>[orig_patent_app_number] => 11415099 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/415099
Wafer level package for surface acoustic wave device and fabrication method thereof May 1, 2006 Issued
Array ( [id] => 5054390 [patent_doc_number] => 20070057311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Conventionally printable non-volatile passive memory element and method of making thereof' [patent_app_type] => utility [patent_app_number] => 11/414428 [patent_app_country] => US [patent_app_date] => 2006-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 12516 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20070057311.pdf [firstpage_image] =>[orig_patent_app_number] => 11414428 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414428
Conventionally printable non-volatile passive memory element and method of making thereof Apr 27, 2006 Abandoned
Array ( [id] => 4985980 [patent_doc_number] => 20070152318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'STRUCTURE AND PROCESS OF CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 11/308658 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20070152318.pdf [firstpage_image] =>[orig_patent_app_number] => 11308658 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308658
STRUCTURE AND PROCESS OF CHIP PACKAGE Apr 18, 2006 Abandoned
Array ( [id] => 4526451 [patent_doc_number] => 07952094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus' [patent_app_type] => utility [patent_app_number] => 11/401338 [patent_app_country] => US [patent_app_date] => 2006-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 10341 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952094.pdf [firstpage_image] =>[orig_patent_app_number] => 11401338 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/401338
Electro-optical device, method of manufacturing electro-optical device, and electronic apparatus Apr 9, 2006 Issued
Array ( [id] => 5869095 [patent_doc_number] => 20060163712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'SYSTEM AND METHOD FOR DIRECT-BONDING OF SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 11/278758 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2354 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163712.pdf [firstpage_image] =>[orig_patent_app_number] => 11278758 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/278758
SYSTEM AND METHOD FOR DIRECT-BONDING OF SUBSTRATES Apr 4, 2006 Abandoned
Array ( [id] => 7504511 [patent_doc_number] => 08035098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-11 [patent_title] => 'Transistor with asymmetric silicon germanium source region' [patent_app_type] => utility [patent_app_number] => 11/278618 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3080 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/035/08035098.pdf [firstpage_image] =>[orig_patent_app_number] => 11278618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/278618
Transistor with asymmetric silicon germanium source region Apr 3, 2006 Issued
Array ( [id] => 5123607 [patent_doc_number] => 20070235877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Integration scheme for semiconductor photodetectors on an integrated circuit chip' [patent_app_type] => utility [patent_app_number] => 11/394818 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20070235877.pdf [firstpage_image] =>[orig_patent_app_number] => 11394818 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394818
Integration scheme for semiconductor photodetectors on an integrated circuit chip Mar 30, 2006 Abandoned
Array ( [id] => 5019621 [patent_doc_number] => 20070145587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'SUBSTRATE WITH MULTI-LAYER INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/308519 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3489 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145587.pdf [firstpage_image] =>[orig_patent_app_number] => 11308519 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308519
SUBSTRATE WITH MULTI-LAYER INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME Mar 30, 2006 Abandoned
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