
Awat M. Salih
Examiner (ID: 18788, Phone: (571)270-5601 , Office: P/2845 )
| Most Active Art Unit | 2845 |
| Art Unit(s) | 2845 |
| Total Applications | 569 |
| Issued Applications | 470 |
| Pending Applications | 50 |
| Abandoned Applications | 69 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5073046
[patent_doc_number] => 20070013021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-01-18
[patent_title] => 'Semiconductor device with a conduction enhancement layer'
[patent_app_type] => utility
[patent_app_number] => 11/157229
[patent_app_country] => US
[patent_app_date] => 2005-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4413
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20070013021.pdf
[firstpage_image] =>[orig_patent_app_number] => 11157229
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/157229 | Semiconductor device with a conduction enhancement layer | Jun 19, 2005 | Issued |
Array
(
[id] => 5909051
[patent_doc_number] => 20060125094
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-15
[patent_title] => 'Solder interconnect on IC chip'
[patent_app_type] => utility
[patent_app_number] => 11/157186
[patent_app_country] => US
[patent_app_date] => 2005-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 80
[patent_figures_cnt] => 80
[patent_no_of_words] => 46066
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0125/20060125094.pdf
[firstpage_image] =>[orig_patent_app_number] => 11157186
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/157186 | Metallization structure over passivation layer for IC chip | Jun 16, 2005 | Issued |
Array
(
[id] => 9350679
[patent_doc_number] => 08669572
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-03-11
[patent_title] => 'Power lamp package'
[patent_app_type] => utility
[patent_app_number] => 11/149998
[patent_app_country] => US
[patent_app_date] => 2005-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 4967
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11149998
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/149998 | Power lamp package | Jun 9, 2005 | Issued |
Array
(
[id] => 326584
[patent_doc_number] => 07514355
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-07
[patent_title] => 'Multilayer interconnection structure and method for forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/149188
[patent_app_country] => US
[patent_app_date] => 2005-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 36
[patent_no_of_words] => 8690
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/514/07514355.pdf
[firstpage_image] =>[orig_patent_app_number] => 11149188
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/149188 | Multilayer interconnection structure and method for forming the same | Jun 9, 2005 | Issued |
Array
(
[id] => 6931289
[patent_doc_number] => 20050282324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-22
[patent_title] => 'Semiconductor device containing distorted silicon layer formed on silicon germanium layer'
[patent_app_type] => utility
[patent_app_number] => 11/148449
[patent_app_country] => US
[patent_app_date] => 2005-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4794
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0282/20050282324.pdf
[firstpage_image] =>[orig_patent_app_number] => 11148449
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/148449 | Semiconductor device containing distorted silicon layer formed on silicon germanium layer | Jun 8, 2005 | Abandoned |
Array
(
[id] => 837303
[patent_doc_number] => 07394120
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-01
[patent_title] => 'Semiconductor device having a shaped gate electrode and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/146029
[patent_app_country] => US
[patent_app_date] => 2005-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 2839
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/394/07394120.pdf
[firstpage_image] =>[orig_patent_app_number] => 11146029
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/146029 | Semiconductor device having a shaped gate electrode and method of manufacturing the same | Jun 6, 2005 | Issued |
Array
(
[id] => 5736068
[patent_doc_number] => 20060006458
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-12
[patent_title] => 'Semiconductor device and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/146129
[patent_app_country] => US
[patent_app_date] => 2005-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7208
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0006/20060006458.pdf
[firstpage_image] =>[orig_patent_app_number] => 11146129
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/146129 | Semiconductor device and method for manufacturing the same | Jun 6, 2005 | Abandoned |
Array
(
[id] => 5884243
[patent_doc_number] => 20060273418
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-07
[patent_title] => '3-D inductor and transformer devices in MRAM embedded integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/147599
[patent_app_country] => US
[patent_app_date] => 2005-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5625
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20060273418.pdf
[firstpage_image] =>[orig_patent_app_number] => 11147599
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/147599 | 3-D inductor and transformer devices in MRAM embedded integrated circuits | Jun 6, 2005 | Issued |
Array
(
[id] => 5884204
[patent_doc_number] => 20060273379
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-07
[patent_title] => 'MOSFET using gate work function engineering for switching applications'
[patent_app_type] => utility
[patent_app_number] => 11/146499
[patent_app_country] => US
[patent_app_date] => 2005-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3402
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20060273379.pdf
[firstpage_image] =>[orig_patent_app_number] => 11146499
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/146499 | MOSFET using gate work function engineering for switching applications | Jun 5, 2005 | Abandoned |
Array
(
[id] => 5659223
[patent_doc_number] => 20060249819
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-09
[patent_title] => 'Lead frame having contacting pins of different thickness'
[patent_app_type] => utility
[patent_app_number] => 11/144639
[patent_app_country] => US
[patent_app_date] => 2005-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1047
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0249/20060249819.pdf
[firstpage_image] =>[orig_patent_app_number] => 11144639
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/144639 | Lead frame having contacting pins of different thickness | Jun 5, 2005 | Abandoned |
Array
(
[id] => 5884266
[patent_doc_number] => 20060273441
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-07
[patent_title] => 'Assembly structure and method for chip scale package'
[patent_app_type] => utility
[patent_app_number] => 11/144719
[patent_app_country] => US
[patent_app_date] => 2005-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1790
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20060273441.pdf
[firstpage_image] =>[orig_patent_app_number] => 11144719
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/144719 | Assembly structure and method for chip scale package | Jun 3, 2005 | Abandoned |
Array
(
[id] => 5605705
[patent_doc_number] => 20060267221
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'Integrated-circuit die having redundant signal pads and related integrated circuit, system, and method'
[patent_app_type] => utility
[patent_app_number] => 11/139248
[patent_app_country] => US
[patent_app_date] => 2005-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6823
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20060267221.pdf
[firstpage_image] =>[orig_patent_app_number] => 11139248
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/139248 | Integrated-circuit die having redundant signal pads and related integrated circuit, system, and method | May 26, 2005 | Abandoned |
Array
(
[id] => 5765737
[patent_doc_number] => 20050263822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 11/138649
[patent_app_country] => US
[patent_app_date] => 2005-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8377
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0263/20050263822.pdf
[firstpage_image] =>[orig_patent_app_number] => 11138649
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/138649 | Semiconductor device and manufacturing method thereof | May 26, 2005 | Abandoned |
Array
(
[id] => 5765833
[patent_doc_number] => 20050263846
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'Circuit device'
[patent_app_type] => utility
[patent_app_number] => 11/139238
[patent_app_country] => US
[patent_app_date] => 2005-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 11062
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0263/20050263846.pdf
[firstpage_image] =>[orig_patent_app_number] => 11139238
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/139238 | Circuit device with dummy elements | May 25, 2005 | Issued |
Array
(
[id] => 865493
[patent_doc_number] => 07368777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Accumulation device with charge balance structure and method of forming the same'
[patent_app_type] => utility
[patent_app_number] => 11/140249
[patent_app_country] => US
[patent_app_date] => 2005-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 6657
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/368/07368777.pdf
[firstpage_image] =>[orig_patent_app_number] => 11140249
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/140249 | Accumulation device with charge balance structure and method of forming the same | May 25, 2005 | Issued |
Array
(
[id] => 5605657
[patent_doc_number] => 20060267173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-30
[patent_title] => 'Integrated circuit package having stacked integrated circuits and method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/140608
[patent_app_country] => US
[patent_app_date] => 2005-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7921
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20060267173.pdf
[firstpage_image] =>[orig_patent_app_number] => 11140608
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/140608 | Integrated circuit package having stacked integrated circuits and method therefor | May 25, 2005 | Abandoned |
Array
(
[id] => 5731417
[patent_doc_number] => 20060256531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Thermal solution with isolation layer'
[patent_app_type] => utility
[patent_app_number] => 11/129158
[patent_app_country] => US
[patent_app_date] => 2005-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3430
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0256/20060256531.pdf
[firstpage_image] =>[orig_patent_app_number] => 11129158
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/129158 | Thermal solution with isolation layer | May 12, 2005 | Abandoned |
Array
(
[id] => 5730328
[patent_doc_number] => 20060255442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'Apparatus and methods for constructing balanced chip packages to reduce thermally induced mechanical strain'
[patent_app_type] => utility
[patent_app_number] => 11/125499
[patent_app_country] => US
[patent_app_date] => 2005-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3720
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0255/20060255442.pdf
[firstpage_image] =>[orig_patent_app_number] => 11125499
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/125499 | Apparatus and methods for constructing balanced chip packages to reduce thermally induced mechanical strain | May 9, 2005 | Issued |
Array
(
[id] => 274213
[patent_doc_number] => 07560377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-14
[patent_title] => 'Plasma processes for depositing low dielectric constant films'
[patent_app_type] => utility
[patent_app_number] => 11/087393
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 33
[patent_no_of_words] => 10935
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/560/07560377.pdf
[firstpage_image] =>[orig_patent_app_number] => 11087393
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/087393 | Plasma processes for depositing low dielectric constant films | Mar 21, 2005 | Issued |
Array
(
[id] => 5664672
[patent_doc_number] => 20060170022
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-03
[patent_title] => 'Silicon molecular hybrid storage cell'
[patent_app_type] => utility
[patent_app_number] => 11/047199
[patent_app_country] => US
[patent_app_date] => 2005-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3132
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0170/20060170022.pdf
[firstpage_image] =>[orig_patent_app_number] => 11047199
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/047199 | Silicon molecular hybrid storage cell | Jan 30, 2005 | Abandoned |