Search

Awat M. Salih

Examiner (ID: 18788, Phone: (571)270-5601 , Office: P/2845 )

Most Active Art Unit
2845
Art Unit(s)
2845
Total Applications
569
Issued Applications
470
Pending Applications
50
Abandoned Applications
69

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17870718 [patent_doc_number] => 20220293455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => WAFER SCALE PACKAGING [patent_app_type] => utility [patent_app_number] => 17/827473 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827473 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827473
WAFER SCALE PACKAGING May 26, 2022 Abandoned
Array ( [id] => 17855194 [patent_doc_number] => 20220285237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => BONDED SUBSTRATE, AND BONDED SUBSTRATE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/752935 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752935
Bonded substrate, and bonded substrate manufacturing method May 24, 2022 Issued
Array ( [id] => 17855194 [patent_doc_number] => 20220285237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => BONDED SUBSTRATE, AND BONDED SUBSTRATE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/752935 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752935
Bonded substrate, and bonded substrate manufacturing method May 24, 2022 Issued
Array ( [id] => 18882877 [patent_doc_number] => 20240006246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => CMOS WELL REGIONS WITH HIGH DOPANT ACTIVATION LEVEL AND REDUCED EXTENDED DEFECTS [patent_app_type] => utility [patent_app_number] => 17/751663 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751663 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751663
CMOS WELL REGIONS WITH HIGH DOPANT ACTIVATION LEVEL AND REDUCED EXTENDED DEFECTS May 23, 2022 Pending
Array ( [id] => 18729355 [patent_doc_number] => 20230343651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => Semiconductor manufacturing process [patent_app_type] => utility [patent_app_number] => 17/752845 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4826 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752845
Semiconductor manufacturing process May 23, 2022 Issued
Array ( [id] => 18882877 [patent_doc_number] => 20240006246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => CMOS WELL REGIONS WITH HIGH DOPANT ACTIVATION LEVEL AND REDUCED EXTENDED DEFECTS [patent_app_type] => utility [patent_app_number] => 17/751663 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751663 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751663
CMOS WELL REGIONS WITH HIGH DOPANT ACTIVATION LEVEL AND REDUCED EXTENDED DEFECTS May 23, 2022 Pending
Array ( [id] => 18209524 [patent_doc_number] => 20230055784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => DISPLAY PANEL INCLUDING A FILLING LAYER [patent_app_type] => utility [patent_app_number] => 17/664860 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664860
DISPLAY PANEL INCLUDING A FILLING LAYER May 23, 2022 Pending
Array ( [id] => 18789655 [patent_doc_number] => 20230378364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => 3D DESIGN WITH METHOD OF INTEGRATION OF HIGH PERFORMANCE TRANSISTORS USING A STREAMLINED PROCESS FLOW [patent_app_type] => utility [patent_app_number] => 17/749957 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749957
3D DESIGN WITH METHOD OF INTEGRATION OF HIGH PERFORMANCE TRANSISTORS USING A STREAMLINED PROCESS FLOW May 19, 2022 Pending
Array ( [id] => 18205543 [patent_doc_number] => 11587949 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-21 [patent_title] => Method of manufacturing semiconductor structure and semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/664246 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 46 [patent_no_of_words] => 6996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664246
Method of manufacturing semiconductor structure and semiconductor structure May 19, 2022 Issued
Array ( [id] => 19945326 [patent_doc_number] => 12317476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Memory structure [patent_app_type] => utility [patent_app_number] => 17/746996 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 3087 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746996 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746996
Memory structure May 17, 2022 Issued
Array ( [id] => 20361695 [patent_doc_number] => 12477712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Memory structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/747064 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 6568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747064
Memory structure and method for manufacturing the same May 17, 2022 Issued
Array ( [id] => 19945326 [patent_doc_number] => 12317476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Memory structure [patent_app_type] => utility [patent_app_number] => 17/746996 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 3087 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746996 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746996
Memory structure May 17, 2022 Issued
Array ( [id] => 19973892 [patent_doc_number] => 12342525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Method for manufacturing semiconductor structure and semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/747314 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747314
Method for manufacturing semiconductor structure and semiconductor structure May 17, 2022 Issued
Array ( [id] => 18759034 [patent_doc_number] => 20230362515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => PHOTOSENSING PIXEL INCLUDING SELF-ALIGNED LIGHT SHIELDING LAYER [patent_app_type] => utility [patent_app_number] => 17/739387 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739387
Photosensing pixel including self-aligned light shielding layer May 8, 2022 Issued
Array ( [id] => 18159970 [patent_doc_number] => 20230026562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/739501 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739501
DISPLAY DEVICE May 8, 2022 Pending
Array ( [id] => 17810851 [patent_doc_number] => 20220262686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD [patent_app_type] => utility [patent_app_number] => 17/739913 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739913
Semiconductor structure and fabrication method May 8, 2022 Issued
Array ( [id] => 18759034 [patent_doc_number] => 20230362515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => PHOTOSENSING PIXEL INCLUDING SELF-ALIGNED LIGHT SHIELDING LAYER [patent_app_type] => utility [patent_app_number] => 17/739387 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739387 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739387
Photosensing pixel including self-aligned light shielding layer May 8, 2022 Issued
Array ( [id] => 19414908 [patent_doc_number] => 12080746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Method for fabricating image sensor [patent_app_type] => utility [patent_app_number] => 17/738409 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 51 [patent_no_of_words] => 14979 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738409
Method for fabricating image sensor May 5, 2022 Issued
Array ( [id] => 19371673 [patent_doc_number] => 12063778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Microelectronic devices including stair step structures, and related electronic devices and methods [patent_app_type] => utility [patent_app_number] => 17/661781 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 14198 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661781
Microelectronic devices including stair step structures, and related electronic devices and methods May 2, 2022 Issued
Array ( [id] => 18164154 [patent_doc_number] => 20230030749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => HYBRID FENCED SUBSTRATE FOR TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATOR FRONTSIDE MEMBRANE RELEASE [patent_app_type] => utility [patent_app_number] => 17/726467 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10509 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726467 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726467
HYBRID FENCED SUBSTRATE FOR TRANSVERSELY-EXCITED FILM BULK ACOUSTIC RESONATOR FRONTSIDE MEMBRANE RELEASE Apr 20, 2022 Pending
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