Search

Azizul Q. Choudhury

Examiner (ID: 5753, Phone: (571)272-3909 , Office: P/2456 )

Most Active Art Unit
2455
Art Unit(s)
2445, 2456, 2145, 2453, 2455, 2143
Total Applications
902
Issued Applications
628
Pending Applications
70
Abandoned Applications
209

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1037231 [patent_doc_number] => 06877125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Devices and methods for estimating a series of symbols' [patent_app_type] => utility [patent_app_number] => 09/953254 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 13455 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877125.pdf [firstpage_image] =>[orig_patent_app_number] => 09953254 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953254
Devices and methods for estimating a series of symbols Sep 16, 2001 Issued
Array ( [id] => 6722480 [patent_doc_number] => 20030056170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Radiation hard divider via single bit correction' [patent_app_type] => new [patent_app_number] => 09/952621 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3485 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056170.pdf [firstpage_image] =>[orig_patent_app_number] => 09952621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952621
Radiation hard divider via single bit correction Sep 13, 2001 Issued
Array ( [id] => 1004807 [patent_doc_number] => 06910175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Encoder redundancy selection system and method' [patent_app_type] => utility [patent_app_number] => 09/952193 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2564 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910175.pdf [firstpage_image] =>[orig_patent_app_number] => 09952193 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952193
Encoder redundancy selection system and method Sep 13, 2001 Issued
Array ( [id] => 7623757 [patent_doc_number] => 06725420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Pattern detection for computer segments' [patent_app_type] => B1 [patent_app_number] => 09/953459 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1548 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725420.pdf [firstpage_image] =>[orig_patent_app_number] => 09953459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953459
Pattern detection for computer segments Sep 13, 2001 Issued
Array ( [id] => 6815078 [patent_doc_number] => 20030074628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Generating log-likelihood values in a maximum a posteriori processor' [patent_app_type] => new [patent_app_number] => 09/951660 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3056 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074628.pdf [firstpage_image] =>[orig_patent_app_number] => 09951660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951660
Generating log-likelihood values in a maximum a posteriori processor Sep 12, 2001 Issued
Array ( [id] => 999138 [patent_doc_number] => 06915444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Network independent safety protocol for industrial controller using data manipulation techniques' [patent_app_type] => utility [patent_app_number] => 09/951251 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 9354 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915444.pdf [firstpage_image] =>[orig_patent_app_number] => 09951251 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951251
Network independent safety protocol for industrial controller using data manipulation techniques Sep 11, 2001 Issued
Array ( [id] => 5861425 [patent_doc_number] => 20020124223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Soft input - soft output forward error correction decoding for turbo codes' [patent_app_type] => new [patent_app_number] => 09/954698 [patent_app_country] => US [patent_app_date] => 2001-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 14858 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124223.pdf [firstpage_image] =>[orig_patent_app_number] => 09954698 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/954698
Soft input-soft output forward error correction decoding for turbo codes Sep 10, 2001 Issued
Array ( [id] => 1068409 [patent_doc_number] => 06848072 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-25 [patent_title] => 'Network processor having cyclic redundancy check implemented in hardware' [patent_app_type] => utility [patent_app_number] => 09/949354 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2869 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/848/06848072.pdf [firstpage_image] =>[orig_patent_app_number] => 09949354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/949354
Network processor having cyclic redundancy check implemented in hardware Sep 6, 2001 Issued
Array ( [id] => 898310 [patent_doc_number] => 07346825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Error method, system and medium' [patent_app_type] => utility [patent_app_number] => 09/948299 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4611 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346825.pdf [firstpage_image] =>[orig_patent_app_number] => 09948299 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948299
Error method, system and medium Sep 5, 2001 Issued
Array ( [id] => 6245485 [patent_doc_number] => 20020046361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Intelligent binning for electrically repairable semiconductor chips' [patent_app_type] => new [patent_app_number] => 09/943777 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6123 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046361.pdf [firstpage_image] =>[orig_patent_app_number] => 09943777 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943777
Intelligent binning for electrically repairable semiconductor chips and method Aug 29, 2001 Issued
Array ( [id] => 7629939 [patent_doc_number] => 06637000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Turbo code interleaver using linear congruential sequences' [patent_app_type] => B2 [patent_app_number] => 09/933979 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8359 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/637/06637000.pdf [firstpage_image] =>[orig_patent_app_number] => 09933979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933979
Turbo code interleaver using linear congruential sequences Aug 19, 2001 Issued
Array ( [id] => 958271 [patent_doc_number] => 06957379 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Method and apparatus for selecting storage capacity of data storage media' [patent_app_type] => utility [patent_app_number] => 09/924064 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10465 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957379.pdf [firstpage_image] =>[orig_patent_app_number] => 09924064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924064
Method and apparatus for selecting storage capacity of data storage media Aug 6, 2001 Issued
Array ( [id] => 6533731 [patent_doc_number] => 20020026607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Medium reading apparatus' [patent_app_type] => new [patent_app_number] => 09/921792 [patent_app_country] => US [patent_app_date] => 2001-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9117 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026607.pdf [firstpage_image] =>[orig_patent_app_number] => 09921792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921792
Medium reading apparatus Aug 5, 2001 Issued
Array ( [id] => 7601890 [patent_doc_number] => 07237156 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-26 [patent_title] => 'Content addressable memory with error detection' [patent_app_type] => utility [patent_app_number] => 09/922423 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 13713 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/237/07237156.pdf [firstpage_image] =>[orig_patent_app_number] => 09922423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922423
Content addressable memory with error detection Aug 2, 2001 Issued
Array ( [id] => 6035689 [patent_doc_number] => 20020019964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Method and device for testing an integrated circuit, integrated circuit to be tested, and wafer with a large number of integrated circuits to be tested' [patent_app_type] => new [patent_app_number] => 09/922479 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9504 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019964.pdf [firstpage_image] =>[orig_patent_app_number] => 09922479 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922479
Method and device for testing an integrated circuit, integrated circuit to be tested, and wafer with a large number of integrated circuits to be tested Aug 2, 2001 Issued
Array ( [id] => 1139343 [patent_doc_number] => 06789221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Integrated circuit with self-test circuit' [patent_app_type] => B2 [patent_app_number] => 09/922140 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2211 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789221.pdf [firstpage_image] =>[orig_patent_app_number] => 09922140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922140
Integrated circuit with self-test circuit Aug 2, 2001 Issued
Array ( [id] => 1197148 [patent_doc_number] => 06732309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method for testing faults in a programmable logic device' [patent_app_type] => B1 [patent_app_number] => 09/921115 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3238 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732309.pdf [firstpage_image] =>[orig_patent_app_number] => 09921115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921115
Method for testing faults in a programmable logic device Aug 1, 2001 Issued
Array ( [id] => 6717486 [patent_doc_number] => 20030028834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Method for sharing redundant rows between banks for improved repair efficiency' [patent_app_type] => new [patent_app_number] => 09/919589 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4035 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028834.pdf [firstpage_image] =>[orig_patent_app_number] => 09919589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919589
Method for sharing redundant rows between banks for improved repair efficiency Jul 31, 2001 Abandoned
Array ( [id] => 6717492 [patent_doc_number] => 20030028840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Quality control in data transfer and storage apparatus' [patent_app_type] => new [patent_app_number] => 09/917769 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6006 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028840.pdf [firstpage_image] =>[orig_patent_app_number] => 09917769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917769
Quality control in data transfer and storage apparatus Jul 30, 2001 Issued
Array ( [id] => 7625675 [patent_doc_number] => 06769092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'Method and system for testing linked list integrity' [patent_app_type] => B1 [patent_app_number] => 09/920270 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5206 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/769/06769092.pdf [firstpage_image] =>[orig_patent_app_number] => 09920270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920270
Method and system for testing linked list integrity Jul 30, 2001 Issued
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