Azizul Q. Choudhury

Array ( [id] => 1314961 [patent_doc_number] => 06622285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Methods and systems for fault location' [patent_app_type] => B1 [patent_app_number] => 09/706315 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/622/06622285.pdf [firstpage_image] =>[orig_patent_app_number] => 09706315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1311808 [patent_doc_number] => 06625769 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method for IC fault analysis using programmable built-in self test and optical emission' [patent_app_type] => B1 [patent_app_number] => 09/703803 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5399 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625769.pdf [firstpage_image] =>[orig_patent_app_number] => 09703803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1272157 [patent_doc_number] => 06662332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Interleaver for burst error correction' [patent_app_type] => B1 [patent_app_number] => 09/704076 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 19368 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662332.pdf [firstpage_image] =>[orig_patent_app_number] => 09704076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1324272 [patent_doc_number] => 06611928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Homo-code continuity proof testing device' [patent_app_type] => B1 [patent_app_number] => 09/703690 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 69 [patent_no_of_words] => 9422 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611928.pdf [firstpage_image] =>[orig_patent_app_number] => 09703690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1295271 [patent_doc_number] => 06640327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Fast BCH error detection and correction using generator polynomial permutation' [patent_app_type] => B1 [patent_app_number] => 09/704390 [patent_app_country] => US [patent_app_date] => 2000-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7489 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/640/06640327.pdf [firstpage_image] =>[orig_patent_app_number] => 09704390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1001807 [patent_doc_number] => 06912678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-28 [patent_title] => 'System for identifying valid connections between electrical system components and responding to invalid connections' [patent_app_type] => utility [patent_app_number] => 09/699392 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6570 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912678.pdf [firstpage_image] =>[orig_patent_app_number] => 09699392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1192675 [patent_doc_number] => 06735730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Integrated circuit with design for testability and method for designing the same' [patent_app_type] => B1 [patent_app_number] => 09/699478 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 40 [patent_no_of_words] => 16683 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735730.pdf [firstpage_image] =>[orig_patent_app_number] => 09699478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7622305 [patent_doc_number] => 06687861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Memory tester with enhanced post decode' [patent_app_type] => B1 [patent_app_number] => 09/702631 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14411 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687861.pdf [firstpage_image] =>[orig_patent_app_number] => 09702631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1184982 [patent_doc_number] => 06748562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Memory tester omits programming of addresses in detected bad columns' [patent_app_type] => B1 [patent_app_number] => 09/702578 [patent_app_country] => US [patent_app_date] => 2000-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14419 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748562.pdf [firstpage_image] =>[orig_patent_app_number] => 09702578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1367024 [patent_doc_number] => 06584588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'System signalling schemes for processor & memory module' [patent_app_type] => B1 [patent_app_number] => 09/698089 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 37 [patent_no_of_words] => 17791 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584588.pdf [firstpage_image] =>[orig_patent_app_number] => 09698089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1272148 [patent_doc_number] => 06662331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Space-efficient turbo decoder' [patent_app_type] => B1 [patent_app_number] => 09/699252 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7788 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/662/06662331.pdf [firstpage_image] =>[orig_patent_app_number] => 09699252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 981792 [patent_doc_number] => 06931581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-16 [patent_title] => 'Method for superimposing a sequence number in an error detection code in a data network' [patent_app_type] => utility [patent_app_number] => 09/697731 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3077 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/931/06931581.pdf [firstpage_image] =>[orig_patent_app_number] => 09697731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430644 [patent_doc_number] => 06526533 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Semiconductor memory implementing internally generated commands' [patent_app_type] => B1 [patent_app_number] => 09/656586 [patent_app_country] => US [patent_app_date] => 2000-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526533.pdf [firstpage_image] =>[orig_patent_app_number] => 09656586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1236602 [patent_doc_number] => 06694475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Magnetic disk apparatus and method of data transfer' [patent_app_type] => B1 [patent_app_number] => 09/581623 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7165 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694475.pdf [firstpage_image] =>[orig_patent_app_number] => 09581623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7633014 [patent_doc_number] => 06658606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method and device for checking an error control procedure of a circuit' [patent_app_type] => B1 [patent_app_number] => 09/530254 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3972 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658606.pdf [firstpage_image] =>[orig_patent_app_number] => 09530254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1260658 [patent_doc_number] => 06668351 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Decoder and decoding method' [patent_app_type] => B1 [patent_app_number] => 09/601976 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8487 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668351.pdf [firstpage_image] =>[orig_patent_app_number] => 09601976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 355659 [patent_doc_number] => 07493540 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-17 [patent_title] => 'Continuous application and decompression of test patterns to a circuit-under-test' [patent_app_type] => utility [patent_app_number] => 09/620021 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6602 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493540.pdf [firstpage_image] =>[orig_patent_app_number] => 09620021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1183890 [patent_doc_number] => 06751772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Rate matching device and method for a data communication system' [patent_app_type] => B1 [patent_app_number] => 09/611014 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12776 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751772.pdf [firstpage_image] =>[orig_patent_app_number] => 09611014 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1407733 [patent_doc_number] => 06560738 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Fault propagation path estimating method, fault propagation path estimating apparatus and recording media' [patent_app_type] => B1 [patent_app_number] => 09/605737 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 13483 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560738.pdf [firstpage_image] =>[orig_patent_app_number] => 09605737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1553179 [patent_doc_number] => 06446229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and apparatus for integrated flip-flop to support two test modes' [patent_app_type] => B1 [patent_app_number] => 09/607184 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446229.pdf [firstpage_image] =>[orig_patent_app_number] => 09607184 [rel_patent_id] =>[rel_patent_doc_number] =>)