Search

Azm A. Parvez

Examiner (ID: 9720, Phone: (571)270-1391 , Office: P/3729 )

Most Active Art Unit
3729
Art Unit(s)
2892, 4136, 3729, 2891
Total Applications
731
Issued Applications
562
Pending Applications
11
Abandoned Applications
164

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20010856 [patent_doc_number] => 20250149078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => DRAM with Analog Refresh Loop [patent_app_type] => utility [patent_app_number] => 18/915412 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18915412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/915412
DRAM with Analog Refresh Loop Oct 14, 2024 Pending
Array ( [id] => 20588396 [patent_doc_number] => 20260073992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => ENABLE OPEN SUB-BLOCK ERASE IN SUB-BLOCK MODE OPERATION [patent_app_type] => utility [patent_app_number] => 18/883214 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883214
ENABLE OPEN SUB-BLOCK ERASE IN SUB-BLOCK MODE OPERATION Sep 11, 2024 Pending
Array ( [id] => 20588381 [patent_doc_number] => 20260073977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => Energy Efficient Compute-in-Memory SRAM-C Circuit Architecture [patent_app_type] => utility [patent_app_number] => 18/883400 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883400 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883400
Energy Efficient Compute-in-Memory SRAM-C Circuit Architecture Sep 11, 2024 Pending
Array ( [id] => 20311739 [patent_doc_number] => 20250329368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => MEMORY DEVICES, SYSTEMS AND REFRESH ADDRESS GENERATION CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/821685 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821685
MEMORY DEVICES, SYSTEMS AND REFRESH ADDRESS GENERATION CIRCUITS Aug 29, 2024 Pending
Array ( [id] => 19820719 [patent_doc_number] => 20250078926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => NON-VOLATILE MEMORY, RELATED INTEGRATED CIRCUIT, ELECTRONIC SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/817969 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817969
NON-VOLATILE MEMORY, RELATED INTEGRATED CIRCUIT, ELECTRONIC SYSTEM AND METHOD Aug 27, 2024 Pending
Array ( [id] => 20124279 [patent_doc_number] => 20250239310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => VOLTAGE ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/813002 [patent_app_country] => US [patent_app_date] => 2024-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18813002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/813002
VOLTAGE ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT Aug 21, 2024 Pending
Array ( [id] => 19634341 [patent_doc_number] => 20240412790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => APPARATUS FOR CAPACITIVE SENSE NAND MEMORY [patent_app_type] => utility [patent_app_number] => 18/806931 [patent_app_country] => US [patent_app_date] => 2024-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18806931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/806931
APPARATUS FOR CAPACITIVE SENSE NAND MEMORY Aug 15, 2024 Pending
Array ( [id] => 19820733 [patent_doc_number] => 20250078940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/794538 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18794538 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/794538
REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES Aug 4, 2024 Pending
Array ( [id] => 20019337 [patent_doc_number] => 20250157559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => STORAGE DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/792554 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18792554 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/792554
STORAGE DEVICE AND OPERATING METHOD THEREOF Aug 1, 2024 Pending
Array ( [id] => 19604442 [patent_doc_number] => 20240395322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => RECONFIGURABLE IN-MEMORY PHYSICALLY UNCLONABLE FUNCTION DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/789837 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18789837 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/789837
RECONFIGURABLE IN-MEMORY PHYSICALLY UNCLONABLE FUNCTION DEVICE AND METHOD OF OPERATING THE SAME Jul 30, 2024 Pending
Array ( [id] => 19604410 [patent_doc_number] => 20240395290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/790426 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790426
STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE Jul 30, 2024 Pending
Array ( [id] => 20222742 [patent_doc_number] => 20250285673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME [patent_app_type] => utility [patent_app_number] => 18/788361 [patent_app_country] => US [patent_app_date] => 2024-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788361 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788361
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME Jul 29, 2024 Pending
Array ( [id] => 20195348 [patent_doc_number] => 20250272058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => Three-Dimensional Phase-Change Memory Array Operable to Perform Multiplication Accumulation Operations [patent_app_type] => utility [patent_app_number] => 18/787950 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8096 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787950 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/787950
Three-Dimensional Phase-Change Memory Array Operable to Perform Multiplication Accumulation Operations Jul 28, 2024 Pending
Array ( [id] => 20283347 [patent_doc_number] => 20250308589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SENSING CIRCUIT IN A VERTICAL MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/788047 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18788047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/788047
SENSING CIRCUIT IN A VERTICAL MEMORY SYSTEM Jul 28, 2024 Pending
Array ( [id] => 19696070 [patent_doc_number] => 20250014615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => MEMORY DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/768111 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768111 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768111
MEMORY DEVICE AND SEMICONDUCTOR DEVICE Jul 9, 2024 Pending
Array ( [id] => 19546139 [patent_doc_number] => 20240363175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY INCLUDING MEMORY CELLS AND A WORD LINE [patent_app_type] => utility [patent_app_number] => 18/768926 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768926
METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY INCLUDING MEMORY CELLS AND A WORD LINE Jul 9, 2024 Pending
Array ( [id] => 19530352 [patent_doc_number] => 20240354254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE [patent_app_type] => utility [patent_app_number] => 18/759068 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759068
APPARATUSES AND METHODS FOR COMPUTE ENABLED CACHE Jun 27, 2024 Pending
Array ( [id] => 19515430 [patent_doc_number] => 20240347116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => PERFORMING BLOCK-LEVEL MEDIA MANAGEMENT OPERATIONS FOR BLOCK STRIPES IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/755046 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755046 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/755046
PERFORMING BLOCK-LEVEL MEDIA MANAGEMENT OPERATIONS FOR BLOCK STRIPES IN A MEMORY DEVICE Jun 25, 2024 Pending
Array ( [id] => 20063058 [patent_doc_number] => 20250201280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/753159 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753159
SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME Jun 24, 2024 Pending
Array ( [id] => 20399083 [patent_doc_number] => 20250374558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => ONE TRANSISTOR-TWO RRAM STRUCTURE AND FABRICATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/752767 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752767 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752767
ONE TRANSISTOR-TWO RRAM STRUCTURE AND FABRICATING METHOD OF THE SAME Jun 23, 2024 Pending
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