
Bac H. Au
Examiner (ID: 17152, Phone: (571)272-8795 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2898 |
| Total Applications | 1269 |
| Issued Applications | 989 |
| Pending Applications | 82 |
| Abandoned Applications | 214 |
Applications
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|---|---|---|---|
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