Search

Bac H. Au

Examiner (ID: 17152, Phone: (571)272-8795 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2822, 2898
Total Applications
1269
Issued Applications
989
Pending Applications
82
Abandoned Applications
214

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17692466 [patent_doc_number] => 20220199759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => DEEP TRENCH CAPACITOR INCLUDING SELF-ALIGNED PLATE CONTACT VIA STRUCTURES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/126294 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126294
Deep trench capacitor including self-aligned plate contact via structures and methods of forming the same Dec 17, 2020 Issued
Array ( [id] => 17758249 [patent_doc_number] => 11398548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/124124 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6095 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124124
Semiconductor device Dec 15, 2020 Issued
Array ( [id] => 16731214 [patent_doc_number] => 20210098362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => Method and Apparatus for Forming Self-Aligned Via with Selectively Deposited Etching Stop Layer [patent_app_type] => utility [patent_app_number] => 17/120601 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120601 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120601
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer Dec 13, 2020 Issued
Array ( [id] => 18236009 [patent_doc_number] => 11600574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Method of forming RDLS and structure formed thereof [patent_app_type] => utility [patent_app_number] => 17/121020 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 9076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121020
Method of forming RDLS and structure formed thereof Dec 13, 2020 Issued
Array ( [id] => 17758131 [patent_doc_number] => 11398430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Package device and a manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/114507 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6840 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114507 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114507
Package device and a manufacturing method thereof Dec 7, 2020 Issued
Array ( [id] => 17787722 [patent_doc_number] => 11410856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Chip packaging method [patent_app_type] => utility [patent_app_number] => 17/109540 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2450 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109540
Chip packaging method Dec 1, 2020 Issued
Array ( [id] => 20347684 [patent_doc_number] => 12471422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Optoelectronic device and method for producing an optoelectronic device [patent_app_type] => utility [patent_app_number] => 17/782545 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/782545
Optoelectronic device and method for producing an optoelectronic device Nov 29, 2020 Issued
Array ( [id] => 16715772 [patent_doc_number] => 20210082919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => Replacement Gate Process for FinFET [patent_app_type] => utility [patent_app_number] => 17/106880 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106880
Replacement gate process for FinFET Nov 29, 2020 Issued
Array ( [id] => 16692100 [patent_doc_number] => 20210074579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 17/101131 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101131
Semiconductor device and method Nov 22, 2020 Issued
Array ( [id] => 16692213 [patent_doc_number] => 20210074692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => INTERPOSER FRAME AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/953871 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953871
Interposer frame and method of manufacturing the same Nov 19, 2020 Issued
Array ( [id] => 17878710 [patent_doc_number] => 11450735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Method of forming guard ring and circuit device [patent_app_type] => utility [patent_app_number] => 16/952305 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952305
Method of forming guard ring and circuit device Nov 18, 2020 Issued
Array ( [id] => 16920420 [patent_doc_number] => 20210193512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => Semiconductor Fabrication Method for Producing Nano-Scaled Electrically Conductive Lines [patent_app_type] => utility [patent_app_number] => 17/081337 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081337 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081337
Semiconductor fabrication method for producing nano-scaled electrically conductive lines Oct 26, 2020 Issued
Array ( [id] => 16624905 [patent_doc_number] => 20210043558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE AND METHOD FOR CREATING A LAYOUT THEREOF [patent_app_type] => utility [patent_app_number] => 17/079952 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079952 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079952
Manufacturing method of a semiconductor device and method for creating a layout thereof Oct 25, 2020 Issued
Array ( [id] => 17978660 [patent_doc_number] => 11495532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Techniques to inhibit delamination from flowable gap-fill dielectric [patent_app_type] => utility [patent_app_number] => 17/078538 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 8420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078538 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/078538
Techniques to inhibit delamination from flowable gap-fill dielectric Oct 22, 2020 Issued
Array ( [id] => 16625076 [patent_doc_number] => 20210043729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => Tiled Lateral BJT [patent_app_type] => utility [patent_app_number] => 17/072777 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072777
Tiled lateral BJT Oct 15, 2020 Issued
Array ( [id] => 17536759 [patent_doc_number] => 20220115368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => INTEGRATED CIRCUIT STRUCTURES WITH WELL BOUNDARY DISTAL TO SUBSTRATE MIDPOINT AND METHODS TO FORM THE SAME [patent_app_type] => utility [patent_app_number] => 17/067033 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067033 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/067033
Integrated circuit structures with well boundary distal to substrate midpoint and methods to form the same Oct 8, 2020 Issued
Array ( [id] => 17509175 [patent_doc_number] => 20220102278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/035160 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035160 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035160
Integrated circuit Sep 27, 2020 Issued
Array ( [id] => 17417055 [patent_doc_number] => 20220051959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => ORGANIC INTERPOSER INCLUDING STRESS-RESISTANT BONDING STRUCTURES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/994711 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994711 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994711
Organic interposer including stress-resistant bonding structures and methods of forming the same Aug 16, 2020 Issued
Array ( [id] => 17389404 [patent_doc_number] => 20220037256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR STRUCTURE HAVING VIA THROUGH BONDED WAFERS AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/983533 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983533
Semiconductor structure having via through bonded wafers and manufacturing method thereof Aug 2, 2020 Issued
Array ( [id] => 16936414 [patent_doc_number] => 20210202303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/983298 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983298 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983298
Semiconductor package and method of manufacturing the same Aug 2, 2020 Issued
Menu