Bac H. Au

Array ( [id] => 16911530 [patent_doc_number] => 11043580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Method of manufacturing semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/808689 [patent_app_country] => US [patent_app_date] => 2020-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 7167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16099157 [patent_doc_number] => 20200203565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => MICRO LIGHT EMITTING DIODE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/807093 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16807093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16936808 [patent_doc_number] => 20210202697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/806366 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16286136 [patent_doc_number] => 20200279738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => SEMICONDUCTOR DEVICES AND FABRICATION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/802891 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17878534 [patent_doc_number] => 11450557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Poisoned metal layer with sloped sidewall for making dual damascene interconnect [patent_app_type] => utility [patent_app_number] => 16/801706 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16801706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16286135 [patent_doc_number] => 20200279737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/800132 [patent_app_country] => US [patent_app_date] => 2020-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16800132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19231248 [patent_doc_number] => 12010902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Manufacturing apparatus and method of manufacturing display apparatus using the same [patent_app_type] => utility [patent_app_number] => 16/792948 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9879 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16792948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16789292 [patent_doc_number] => 10991731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/782455 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 69 [patent_no_of_words] => 16959 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17010913 [patent_doc_number] => 20210242074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SELECTIVE DEPOSITION OF CONDUCTIVE CAP FOR FULLY-ALIGNED-VIA (FAV) [patent_app_type] => utility [patent_app_number] => 16/782344 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17224671 [patent_doc_number] => 11177181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Scalable device for FINFET technology [patent_app_type] => utility [patent_app_number] => 16/743980 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 8732 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15906683 [patent_doc_number] => 20200152862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => MAGNETORESISTANCE EFFECT ELEMENT [patent_app_type] => utility [patent_app_number] => 16/739521 [patent_app_country] => US [patent_app_date] => 2020-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16536780 [patent_doc_number] => 10879395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Method for forming semiconductor device structure with cap layer [patent_app_type] => utility [patent_app_number] => 16/730415 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16936586 [patent_doc_number] => 20210202475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => THREE DIMENSIONAL INTEGRATED CIRCUIT AND FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 16/727395 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727395 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15841283 [patent_doc_number] => 20200135924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => FINFET HAVING A RELAXATION PREVENTION ANCHOR AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 16/726540 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15775903 [patent_doc_number] => 20200118969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => Methods for Controlling Warpage in Packaging [patent_app_type] => utility [patent_app_number] => 16/715605 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15776309 [patent_doc_number] => 20200119172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => ADVANCED WAFER BONDED HETEROJUNCTION BIPOLAR TRANSISTORS AND METHODS OF MANUFACTURE OF ADVANCED WAFER BONDED HETEROJUNCTION BIPOLAR TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/708093 [patent_app_country] => US [patent_app_date] => 2019-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 45574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16708093 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16999285 [patent_doc_number] => 11078074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Integration scheme for microelectromechanical systems (MEMS) devices and complementary metal-oxide-semiconductor (CMOS) devices [patent_app_type] => utility [patent_app_number] => 16/705591 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 87 [patent_no_of_words] => 15768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15775697 [patent_doc_number] => 20200118866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => CONTROLLING PERFORMANCE AND RELIABILITY OF CONDUCTIVE REGIONS IN A METALLIZATION NETWORK [patent_app_type] => utility [patent_app_number] => 16/699934 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16881144 [patent_doc_number] => 11031301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages [patent_app_type] => utility [patent_app_number] => 16/691803 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7544 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16691803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15657651 [patent_doc_number] => 20200091356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => LASER BEAM SHAPING FOR FOIL-BASED METALLIZATION OF SOLAR CELLS [patent_app_type] => utility [patent_app_number] => 16/686016 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16686016 [rel_patent_id] =>[rel_patent_doc_number] =>)