
Bac H. Au
Examiner (ID: 14002, Phone: (571)272-8795 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2898 |
| Total Applications | 1265 |
| Issued Applications | 989 |
| Pending Applications | 78 |
| Abandoned Applications | 214 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 12728125
[patent_doc_number] => 20180134542
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-17
[patent_title] => METHOD AND APPARATUS FOR REDUCING IN-PROCESS AND IN-USE STICTION FOR MEMS DEVICES
[patent_app_type] => utility
[patent_app_number] => 15/850677
[patent_app_country] => US
[patent_app_date] => 2017-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4934
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850677
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/850677 | Method and apparatus for reducing in-process and in-use stiction for MEMS devices | Dec 20, 2017 | Issued |
Array
(
[id] => 15922729
[patent_doc_number] => 10658615
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-19
[patent_title] => Display device
[patent_app_type] => utility
[patent_app_number] => 15/837293
[patent_app_country] => US
[patent_app_date] => 2017-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 16
[patent_no_of_words] => 9378
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837293
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/837293 | Display device | Dec 10, 2017 | Issued |
Array
(
[id] => 14446433
[patent_doc_number] => 20190181090
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => FINFET FUSES FORMED AT TIGHT PITCH DIMENSIONS
[patent_app_type] => utility
[patent_app_number] => 15/836339
[patent_app_country] => US
[patent_app_date] => 2017-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6984
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15836339
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/836339 | FinFET fuses formed at tight pitch dimensions | Dec 7, 2017 | Issued |
Array
(
[id] => 14644729
[patent_doc_number] => 10367115
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-30
[patent_title] => Method of manufacturing solar cell
[patent_app_type] => utility
[patent_app_number] => 15/832321
[patent_app_country] => US
[patent_app_date] => 2017-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 7926
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15832321
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/832321 | Method of manufacturing solar cell | Dec 4, 2017 | Issued |
Array
(
[id] => 12263793
[patent_doc_number] => 20180082989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'THREE DIMENSIONAL INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 15/829442
[patent_app_country] => US
[patent_app_date] => 2017-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 15745
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829442
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/829442 | Three dimensional integrated circuit | Nov 30, 2017 | Issued |
Array
(
[id] => 12595827
[patent_doc_number] => 20180090439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => HYBRID COPPER STRUCTURE FOR ADVANCE INTERCONNECT USAGE
[patent_app_type] => utility
[patent_app_number] => 15/819280
[patent_app_country] => US
[patent_app_date] => 2017-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4534
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819280
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/819280 | Hybrid copper structure for advance interconnect usage | Nov 20, 2017 | Issued |
Array
(
[id] => 12223346
[patent_doc_number] => 20180061706
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-01
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING A Pd-CONTAINING ADHESION LAYER'
[patent_app_type] => utility
[patent_app_number] => 15/804558
[patent_app_country] => US
[patent_app_date] => 2017-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4182
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804558
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/804558 | Semiconductor device having a Pd-containing adhesion layer | Nov 5, 2017 | Issued |
Array
(
[id] => 13951291
[patent_doc_number] => 10211430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-19
[patent_title] => Method of manufacturing organic light-emitting display device
[patent_app_type] => utility
[patent_app_number] => 15/803131
[patent_app_country] => US
[patent_app_date] => 2017-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8069
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803131
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/803131 | Method of manufacturing organic light-emitting display device | Nov 2, 2017 | Issued |
Array
(
[id] => 14284979
[patent_doc_number] => 20190139774
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => TRANSPARENT HALO FOR REDUCED PARTICLE GENERATION
[patent_app_type] => utility
[patent_app_number] => 15/803242
[patent_app_country] => US
[patent_app_date] => 2017-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4913
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803242
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/803242 | Transparent halo for reduced particle generation | Nov 2, 2017 | Issued |
Array
(
[id] => 16173018
[patent_doc_number] => 10714598
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-14
[patent_title] => Method of manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/801128
[patent_app_country] => US
[patent_app_date] => 2017-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 22
[patent_no_of_words] => 7155
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801128
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/801128 | Method of manufacturing semiconductor device | Oct 31, 2017 | Issued |
Array
(
[id] => 14205005
[patent_doc_number] => 10269624
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => Contact plugs and methods of forming same
[patent_app_type] => utility
[patent_app_number] => 15/801154
[patent_app_country] => US
[patent_app_date] => 2017-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 40
[patent_no_of_words] => 9397
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801154
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/801154 | Contact plugs and methods of forming same | Oct 31, 2017 | Issued |
Array
(
[id] => 13452261
[patent_doc_number] => 20180277673
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-09-27
[patent_title] => Termination Region Architecture for Vertical Power Transistors
[patent_app_type] => utility
[patent_app_number] => 15/786246
[patent_app_country] => US
[patent_app_date] => 2017-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11197
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786246
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/786246 | Termination region architecture for vertical power transistors | Oct 16, 2017 | Issued |
Array
(
[id] => 13893969
[patent_doc_number] => 10199541
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-02-05
[patent_title] => Light-emitting device
[patent_app_type] => utility
[patent_app_number] => 15/722551
[patent_app_country] => US
[patent_app_date] => 2017-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 5852
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722551
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/722551 | Light-emitting device | Oct 1, 2017 | Issued |
Array
(
[id] => 13667223
[patent_doc_number] => 10163790
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-25
[patent_title] => Manufacturing method of a semiconductor device and method for creating a layout thereof
[patent_app_type] => utility
[patent_app_number] => 15/719135
[patent_app_country] => US
[patent_app_date] => 2017-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 61
[patent_no_of_words] => 9343
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719135
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/719135 | Manufacturing method of a semiconductor device and method for creating a layout thereof | Sep 27, 2017 | Issued |
Array
(
[id] => 12122307
[patent_doc_number] => 20180005893
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'METHODS FOR FORMING MASK LAYERS USING A FLOWABLE CARBON-CONTAINING SILICON DIOXIDE MATERIAL'
[patent_app_type] => utility
[patent_app_number] => 15/703601
[patent_app_country] => US
[patent_app_date] => 2017-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3449
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703601
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/703601 | METHODS FOR FORMING MASK LAYERS USING A FLOWABLE CARBON-CONTAINING SILICON DIOXIDE MATERIAL | Sep 12, 2017 | Abandoned |
Array
(
[id] => 13848127
[patent_doc_number] => 20190027548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-01-24
[patent_title] => METHOD FOR MANUFACTURING ARRAY SUBSTRATE OF AMOLED DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/580985
[patent_app_country] => US
[patent_app_date] => 2017-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2997
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 331
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15580985
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/580985 | METHOD FOR MANUFACTURING ARRAY SUBSTRATE OF AMOLED DEVICE | Sep 10, 2017 | Abandoned |
Array
(
[id] => 12236212
[patent_doc_number] => 20180069075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-08
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/687558
[patent_app_country] => US
[patent_app_date] => 2017-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5118
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687558
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687558 | Semiconductor device | Aug 27, 2017 | Issued |
Array
(
[id] => 13271241
[patent_doc_number] => 10147707
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-12-04
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/687378
[patent_app_country] => US
[patent_app_date] => 2017-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4637
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687378
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687378 | Semiconductor device | Aug 24, 2017 | Issued |
Array
(
[id] => 15889897
[patent_doc_number] => 10651306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-12
[patent_title] => Digital alloy based back barrier for P-channel nitride transistors
[patent_app_type] => utility
[patent_app_number] => 15/687369
[patent_app_country] => US
[patent_app_date] => 2017-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 4198
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687369
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687369 | Digital alloy based back barrier for P-channel nitride transistors | Aug 24, 2017 | Issued |
Array
(
[id] => 12243254
[patent_doc_number] => 20180076118
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-15
[patent_title] => 'SEMICONDUCTOR DEVICE PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 15/687076
[patent_app_country] => US
[patent_app_date] => 2017-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6962
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687076
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687076 | SEMICONDUCTOR DEVICE PACKAGE | Aug 24, 2017 | Abandoned |