Search

Bac H. Au

Examiner (ID: 7814, Phone: (571)272-8795 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2822
Total Applications
1256
Issued Applications
978
Pending Applications
82
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11840051 [patent_doc_number] => 20170221772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'System and Method for a Field-Effect Transistor with Dual Vertical Gates' [patent_app_type] => utility [patent_app_number] => 15/485846 [patent_app_country] => US [patent_app_date] => 2017-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15485846 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/485846
System and method for a field-effect transistor with dual vertical gates Apr 11, 2017 Issued
Array ( [id] => 13514799 [patent_doc_number] => 20180308942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => MANUFACTURING METHOD OF ELECTRODE LAYER OF TFT SUBSTRATE AND MANUFACTURING METHOD OF FLEXIBLE TFT SUBSTRATE [patent_app_type] => utility [patent_app_number] => 15/529509 [patent_app_country] => US [patent_app_date] => 2017-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15529509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/529509
MANUFACTURING METHOD OF ELECTRODE LAYER OF TFT SUBSTRATE AND MANUFACTURING METHOD OF FLEXIBLE TFT SUBSTRATE Apr 10, 2017 Abandoned
Array ( [id] => 11732974 [patent_doc_number] => 20170194417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'METHODS FOR PRODUCING POLYSILICON RESISTORS' [patent_app_type] => utility [patent_app_number] => 15/465715 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7883 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15465715 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/465715
METHODS FOR PRODUCING POLYSILICON RESISTORS Mar 21, 2017 Abandoned
Array ( [id] => 15389161 [patent_doc_number] => 10535785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Laser beam shaping for foil-based metallization of solar cells [patent_app_type] => utility [patent_app_number] => 15/454890 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7852 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15454890 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/454890
Laser beam shaping for foil-based metallization of solar cells Mar 8, 2017 Issued
Array ( [id] => 12250299 [patent_doc_number] => 09923082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Junction butting structure using nonuniform trench shape' [patent_app_type] => utility [patent_app_number] => 15/453939 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6141 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15453939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/453939
Junction butting structure using nonuniform trench shape Mar 8, 2017 Issued
Array ( [id] => 12202614 [patent_doc_number] => 09905687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Semiconductor device and method of making' [patent_app_type] => utility [patent_app_number] => 15/435694 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 7755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15435694 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/435694
Semiconductor device and method of making Feb 16, 2017 Issued
Array ( [id] => 11869555 [patent_doc_number] => 20170236839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-17 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/420628 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 67 [patent_figures_cnt] => 67 [patent_no_of_words] => 54122 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420628 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/420628
Semiconductor device and method for manufacturing the same Jan 30, 2017 Issued
Array ( [id] => 13334907 [patent_doc_number] => 20180218991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => METHODS OF FORMING INTEGRATED CIRCUIT STRUCTURE FOR JOINING WAFERS AND RESULTING STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/420362 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4512 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420362 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/420362
Methods of forming integrated circuit structure for joining wafers and resulting structure Jan 30, 2017 Issued
Array ( [id] => 14036075 [patent_doc_number] => 10229791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Method for preparing a bonded type perovskite solar cell [patent_app_type] => utility [patent_app_number] => 15/419604 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6277 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419604 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419604
Method for preparing a bonded type perovskite solar cell Jan 29, 2017 Issued
Array ( [id] => 12396540 [patent_doc_number] => 09966438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Method of doped germanium formation [patent_app_type] => utility [patent_app_number] => 15/418286 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6387 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15418286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/418286
Method of doped germanium formation Jan 26, 2017 Issued
Array ( [id] => 11840365 [patent_doc_number] => 20170222085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'METHOD OF MANUFACTURING SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 15/418336 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15418336 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/418336
Method of manufacturing solar cell Jan 26, 2017 Issued
Array ( [id] => 13043055 [patent_doc_number] => 10043667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Integrated method for wafer outgassing reduction [patent_app_type] => utility [patent_app_number] => 15/418190 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15418190 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/418190
Integrated method for wafer outgassing reduction Jan 26, 2017 Issued
Array ( [id] => 11623299 [patent_doc_number] => 20170133487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Replacement Gate Process for FinFET' [patent_app_type] => utility [patent_app_number] => 15/415641 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6241 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15415641 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/415641
Replacement gate process for FinFET Jan 24, 2017 Issued
Array ( [id] => 11854892 [patent_doc_number] => 20170229384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'METHOD OF MANUFACTURING ELEMENT CHIP, METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE, AND ELECTRONIC COMPONENT-MOUNTED STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/408750 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5842 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408750 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408750
Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and electronic component-mounted structure Jan 17, 2017 Issued
Array ( [id] => 12012700 [patent_doc_number] => 09806021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Manufacturing method of a semiconductor device and method for creating a layout thereof' [patent_app_type] => utility [patent_app_number] => 15/408562 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 60 [patent_no_of_words] => 9425 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408562 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408562
Manufacturing method of a semiconductor device and method for creating a layout thereof Jan 17, 2017 Issued
Array ( [id] => 12202586 [patent_doc_number] => 09905657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Semiconductor device and method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/408719 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 169 [patent_no_of_words] => 45893 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408719
Semiconductor device and method for manufacturing semiconductor device Jan 17, 2017 Issued
Array ( [id] => 13006299 [patent_doc_number] => 10026824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-17 [patent_title] => Air-gap gate sidewall spacer and method [patent_app_type] => utility [patent_app_number] => 15/408540 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 9204 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408540 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408540
Air-gap gate sidewall spacer and method Jan 17, 2017 Issued
Array ( [id] => 13228999 [patent_doc_number] => 10128282 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/407287 [patent_app_country] => US [patent_app_date] => 2017-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 69 [patent_no_of_words] => 16959 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15407287 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/407287
Method for manufacturing semiconductor device Jan 16, 2017 Issued
Array ( [id] => 12229854 [patent_doc_number] => 09917103 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-13 [patent_title] => 'Diffusion break forming after source/drain forming and related IC structure' [patent_app_type] => utility [patent_app_number] => 15/397978 [patent_app_country] => US [patent_app_date] => 2017-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7163 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397978 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/397978
Diffusion break forming after source/drain forming and related IC structure Jan 3, 2017 Issued
Array ( [id] => 15984713 [patent_doc_number] => 10672694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Printed circuit board, semiconductor package including the printed circuit board, and method of manufacturing the printed circuit board [patent_app_type] => utility [patent_app_number] => 15/397970 [patent_app_country] => US [patent_app_date] => 2017-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 17386 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397970 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/397970
Printed circuit board, semiconductor package including the printed circuit board, and method of manufacturing the printed circuit board Jan 3, 2017 Issued
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