Search

Bac H. Au

Examiner (ID: 11304, Phone: (571)272-8795 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2898, 2822
Total Applications
1231
Issued Applications
975
Pending Applications
66
Abandoned Applications
213

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19500383 [patent_doc_number] => 20240339401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR DEVICE WITH FILLING LAYER AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/234042 [patent_app_country] => US [patent_app_date] => 2023-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234042 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/234042
SEMICONDUCTOR DEVICE WITH FILLING LAYER AND METHOD FOR FABRICATING THE SAME Aug 14, 2023 Pending
Array ( [id] => 20375210 [patent_doc_number] => 12482654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => System and method for multiple step directional patterning [patent_app_type] => utility [patent_app_number] => 18/447869 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 3383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447869 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447869
System and method for multiple step directional patterning Aug 9, 2023 Issued
Array ( [id] => 18991049 [patent_doc_number] => 20240063018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/366470 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366470
METHOD OF FABRICATING SEMICONDUCTOR DEVICE Aug 6, 2023 Pending
Array ( [id] => 18849070 [patent_doc_number] => 20230411474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 18/366369 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11416 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366369 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366369
Semiconductor device and method Aug 6, 2023 Issued
Array ( [id] => 19664436 [patent_doc_number] => 12178144 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Top electrode last scheme for memory cell to prevent metal redeposit [patent_app_type] => utility [patent_app_number] => 18/362067 [patent_app_country] => US [patent_app_date] => 2023-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362067 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362067
Top electrode last scheme for memory cell to prevent metal redeposit Jul 30, 2023 Issued
Array ( [id] => 18757457 [patent_doc_number] => 20230360919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => WAFER THINNING METHOD HAVING FEEDBACK CONTROL [patent_app_type] => utility [patent_app_number] => 18/356388 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356388 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356388
WAFER THINNING METHOD HAVING FEEDBACK CONTROL Jul 20, 2023 Pending
Array ( [id] => 19943636 [patent_doc_number] => 12315772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/355379 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 2194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355379 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355379
Package and manufacturing method thereof Jul 18, 2023 Issued
Array ( [id] => 19436181 [patent_doc_number] => 20240304679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SELECTIVE SIN CAPPING ON METAL GATE FOR METAL OXIDATION PREVENTION [patent_app_type] => utility [patent_app_number] => 18/348868 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348868 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348868
SELECTIVE SIN CAPPING ON METAL GATE FOR METAL OXIDATION PREVENTION Jul 6, 2023 Pending
Array ( [id] => 18757698 [patent_doc_number] => 20230361161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/347850 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10823 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347850 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347850
Semiconductor device Jul 5, 2023 Issued
Array ( [id] => 19436042 [patent_doc_number] => 20240304540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/348211 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348211 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348211
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE Jul 5, 2023 Pending
Array ( [id] => 20175490 [patent_doc_number] => 12394242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Fingerprint sensor device and method [patent_app_type] => utility [patent_app_number] => 18/343036 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343036 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343036
Fingerprint sensor device and method Jun 27, 2023 Issued
Array ( [id] => 18743425 [patent_doc_number] => 20230352413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR DEVICES WITH RECESSED PADS FOR DIE STACK INTERCONNECTIONS [patent_app_type] => utility [patent_app_number] => 18/214378 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214378 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/214378
Semiconductor devices with recessed pads for die stack interconnections Jun 25, 2023 Issued
Array ( [id] => 18712975 [patent_doc_number] => 20230335608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/341100 [patent_app_country] => US [patent_app_date] => 2023-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18341100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/341100
Semiconductor structure Jun 25, 2023 Issued
Array ( [id] => 19733786 [patent_doc_number] => 12211788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Hybrid interconnect structure for self aligned via [patent_app_type] => utility [patent_app_number] => 18/340079 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 6708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340079 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340079
Hybrid interconnect structure for self aligned via Jun 22, 2023 Issued
Array ( [id] => 18712802 [patent_doc_number] => 20230335435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/338730 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15475 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338730
INTEGRATED CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF Jun 20, 2023 Pending
Array ( [id] => 19662091 [patent_doc_number] => 20240429156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => Embedding Metal-Insulator-Metal Structure In Silicon Oxide In A Copper Redistribution Layer Scheme [patent_app_type] => utility [patent_app_number] => 18/337963 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337963 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337963
Embedding Metal-Insulator-Metal Structure In Silicon Oxide In A Copper Redistribution Layer Scheme Jun 19, 2023 Pending
Array ( [id] => 19646549 [patent_doc_number] => 20240421069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => TIGHT PITCH DIRECTIONAL SELECTIVE VIA GROWTH [patent_app_type] => utility [patent_app_number] => 18/211283 [patent_app_country] => US [patent_app_date] => 2023-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211283 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/211283
TIGHT PITCH DIRECTIONAL SELECTIVE VIA GROWTH Jun 17, 2023 Pending
Array ( [id] => 19646470 [patent_doc_number] => 20240420990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SEMICONDUCTOR BACKSIDE ISOLATION FEATURE FOR MERGED EPITAXY [patent_app_type] => utility [patent_app_number] => 18/336063 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336063 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336063
SEMICONDUCTOR BACKSIDE ISOLATION FEATURE FOR MERGED EPITAXY Jun 15, 2023 Pending
Array ( [id] => 19646556 [patent_doc_number] => 20240421076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => ADVANCED INTERCONNECTS WITH HYPERBOLOID PROFILE [patent_app_type] => utility [patent_app_number] => 18/333642 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333642 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333642
ADVANCED INTERCONNECTS WITH HYPERBOLOID PROFILE Jun 12, 2023 Pending
Array ( [id] => 19559907 [patent_doc_number] => 20240371699 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/208896 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4291 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18208896 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/208896
Semiconductor structure and manufacturing method thereof Jun 12, 2023 Pending
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