
Bac H. Au
Examiner (ID: 17152, Phone: (571)272-8795 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2822, 2898 |
| Total Applications | 1269 |
| Issued Applications | 989 |
| Pending Applications | 82 |
| Abandoned Applications | 214 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20900750
[patent_doc_number] => 12708033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-11
[patent_title] => Power semiconductor module arrangement and method for assembling the same
[patent_app_type] => utility
[patent_app_number] => 18/504463
[patent_app_country] => US
[patent_app_date] => 2023-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 22
[patent_no_of_words] => 1160
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 247
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504463
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/504463 | POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR ASSEMBLING THE SAME | Nov 7, 2023 | Pending |
Array
(
[id] => 19191538
[patent_doc_number] => 20240170451
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-23
[patent_title] => ASSEMBLY OF INTEGRATED CIRCUIT WAFERS
[patent_app_type] => utility
[patent_app_number] => 18/504895
[patent_app_country] => US
[patent_app_date] => 2023-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5137
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504895
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/504895 | ASSEMBLY OF INTEGRATED CIRCUIT WAFERS | Nov 7, 2023 | Pending |
Array
(
[id] => 19470673
[patent_doc_number] => 20240324343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/504322
[patent_app_country] => US
[patent_app_date] => 2023-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10216
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504322
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/504322 | Display device | Nov 7, 2023 | Issued |
Array
(
[id] => 20011277
[patent_doc_number] => 20250149499
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => HYBRID BONDING WITH SELECTIVELY FORMED DIELECTRIC MATERIAL
[patent_app_type] => utility
[patent_app_number] => 18/504526
[patent_app_country] => US
[patent_app_date] => 2023-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18504526
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/504526 | HYBRID BONDING WITH SELECTIVELY FORMED DIELECTRIC MATERIAL | Nov 7, 2023 | Pending |
Array
(
[id] => 19148694
[patent_doc_number] => 20240147815
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => DISPLAY APPARATUS WITH IMPROVED ADHESION CHARACTERISTICS IN NON-ACTIVE AREA
[patent_app_type] => utility
[patent_app_number] => 18/384687
[patent_app_country] => US
[patent_app_date] => 2023-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384687
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/384687 | DISPLAY APPARATUS WITH IMPROVED ADHESION CHARACTERISTICS IN NON-ACTIVE AREA | Oct 26, 2023 | Pending |
Array
(
[id] => 19606819
[patent_doc_number] => 20240397699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-28
[patent_title] => CAPACITORLESS 3D STACKED DRAM DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/570810
[patent_app_country] => US
[patent_app_date] => 2023-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11193
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18570810
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/570810 | CAPACITORLESS 3D STACKED DRAM DEVICE AND MANUFACTURING METHOD THEREOF | Oct 16, 2023 | Pending |
Array
(
[id] => 20276507
[patent_doc_number] => 12446296
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-14
[patent_title] => Etch profile control of via opening
[patent_app_type] => utility
[patent_app_number] => 18/481120
[patent_app_country] => US
[patent_app_date] => 2023-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 59
[patent_figures_cnt] => 59
[patent_no_of_words] => 11360
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481120
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/481120 | Etch profile control of via opening | Oct 3, 2023 | Issued |
Array
(
[id] => 18906041
[patent_doc_number] => 20240021526
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-18
[patent_title] => INTEGRATED CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/474822
[patent_app_country] => US
[patent_app_date] => 2023-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 29322
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474822
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/474822 | Integrated circuit | Sep 25, 2023 | Issued |
Array
(
[id] => 18898714
[patent_doc_number] => 20240014199
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-11
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 18/472249
[patent_app_country] => US
[patent_app_date] => 2023-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6573
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472249
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/472249 | Semiconductor package | Sep 21, 2023 | Issued |
Array
(
[id] => 20692073
[patent_doc_number] => 12622249
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-05-05
[patent_title] => Method of manufacturing semiconductor structure including a planarization and semiconductor structure thereof
[patent_app_type] => utility
[patent_app_number] => 18/235970
[patent_app_country] => US
[patent_app_date] => 2023-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 3373
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18235970
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/235970 | Method of manufacturing semiconductor structure including a planarization and semiconductor structure thereof | Aug 20, 2023 | Issued |
Array
(
[id] => 20793021
[patent_doc_number] => 12666955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-23
[patent_title] => Semiconductor device with filling layer and method for fabricating the same
[patent_app_type] => utility
[patent_app_number] => 18/234042
[patent_app_country] => US
[patent_app_date] => 2023-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 4563
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18234042
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/234042 | Semiconductor device with filling layer and method for fabricating the same | Aug 14, 2023 | Issued |
Array
(
[id] => 18812575
[patent_doc_number] => 20230386912
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-30
[patent_title] => Contact Structure For Semiconductor Device
[patent_app_type] => utility
[patent_app_number] => 18/232718
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9860
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18232718
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/232718 | Contact Structure For Semiconductor Device | Aug 9, 2023 | Pending |
Array
(
[id] => 20375210
[patent_doc_number] => 12482654
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-25
[patent_title] => System and method for multiple step directional patterning
[patent_app_type] => utility
[patent_app_number] => 18/447869
[patent_app_country] => US
[patent_app_date] => 2023-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 26
[patent_no_of_words] => 3383
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447869
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/447869 | System and method for multiple step directional patterning | Aug 9, 2023 | Issued |
Array
(
[id] => 18849070
[patent_doc_number] => 20230411474
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-21
[patent_title] => Semiconductor Device and Method
[patent_app_type] => utility
[patent_app_number] => 18/366369
[patent_app_country] => US
[patent_app_date] => 2023-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11416
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366369
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/366369 | Semiconductor device and method | Aug 6, 2023 | Issued |
Array
(
[id] => 18991049
[patent_doc_number] => 20240063018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => METHOD OF FABRICATING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/366470
[patent_app_country] => US
[patent_app_date] => 2023-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9655
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366470
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/366470 | Method of fabricating semiconductor device | Aug 6, 2023 | Issued |
Array
(
[id] => 19773383
[patent_doc_number] => 20250054809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-13
[patent_title] => FULLY SELF-ALIGNED VIA WITH GRAPHENE CAP
[patent_app_type] => utility
[patent_app_number] => 18/366492
[patent_app_country] => US
[patent_app_date] => 2023-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8792
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366492
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/366492 | FULLY SELF-ALIGNED VIA WITH GRAPHENE CAP | Aug 6, 2023 | Pending |
Array
(
[id] => 19007845
[patent_doc_number] => 20240071916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-29
[patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/364487
[patent_app_country] => US
[patent_app_date] => 2023-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7223
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364487
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/364487 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE | Aug 2, 2023 | Pending |
Array
(
[id] => 19664436
[patent_doc_number] => 12178144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-12-24
[patent_title] => Top electrode last scheme for memory cell to prevent metal redeposit
[patent_app_type] => utility
[patent_app_number] => 18/362067
[patent_app_country] => US
[patent_app_date] => 2023-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 7019
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362067
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/362067 | Top electrode last scheme for memory cell to prevent metal redeposit | Jul 30, 2023 | Issued |
Array
(
[id] => 20916990
[patent_doc_number] => 12713859
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-08-18
[patent_title] => Wafer thinning method having feedback control
[patent_app_type] => utility
[patent_app_number] => 18/356388
[patent_app_country] => US
[patent_app_date] => 2023-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 1066
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356388
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/356388 | WAFER THINNING METHOD HAVING FEEDBACK CONTROL | Jul 20, 2023 | Pending |
Array
(
[id] => 19943636
[patent_doc_number] => 12315772
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Package and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 18/355379
[patent_app_country] => US
[patent_app_date] => 2023-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 2194
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355379
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/355379 | Package and manufacturing method thereof | Jul 18, 2023 | Issued |